Systems and methods for storing information
AssigneeInfineon Technologies AG
InventorsMihai-Alexandru Ionescu, Christoph Schroers, Davide Cassata, Hubert Fischer, Wolfgang Horn, Razvan-Catalin Mialtu, Radu Mihaescu
Life of this patent
Estimating the term…
Abstract
An information storage circuit having a first memory portion configured to store a first validity bit and first data; a second memory portion configured to store a second validity bit and second data; and a subcircuit configured to: write the first data to the first memory portion and the second data to the second memory portion sequentially; and set the first and second validity bits to indicate which of the first data and second data is valid.
Claims17
An information storage circuit, comprising:
- a first memory configured to store a first validity bit and first data;
- a first supply domain coupled to the first memory and configured to supply power to the first memory via at least a first capacitor during power loss;
- a second memory configured to store a second validity bit and second data;
- a second supply domain coupled to the second memory and configured to supply power to the second memory via at least a second capacitor during power loss, the first capacitor being different from the second capacitor;
- a subcircuit configured to:
- set the first validity bit of the first memory to invalid,
- write the first data to the first memory while the first validity bit is set to invalid, and
- reset the first validity bit of the first memory as valid, indicating that the written first data is valid,
- wherein the subcircuit is configured to write the first data to the first memory and the second data to the second memory sequentially;
- and
- a logic configured to determine during a start-up the settings of the first and second validity bits.
A method for storing information in first and second memories configured to store first and second validity bits, respectively, the method comprising:
- by a first supply domain coupled to the first memory, supplying power to the first memory via at least a first capacitor during power loss;
- by a second supply domain coupled to the second memory, supplying power to the second memory via at least a second capacitor during power loss, the first capacitor being different from the second capacitor;
- setting the first validity bit of the first memory to invalid;
- writing first data to the first memory while the first validity bit is set to invalid;
- resetting the first validity bit of the first memory to valid, indicating that the written first data is valid,
- wherein valid data is stored in at least one of the first and second memories;
- and
- determining, by a logic during a start-up, the settings of the first and second validity bits.
Dependencies are inferred from the claim text.