# US 10,485,111 B2 · Via and skip via structures

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- Number: US 10,485,111 B2
- Document ID: US10485111B2
- Status: Granted
- Kind: B2
- Application number: 15/647,400
- Filed: 2017-07-12
- Published: 2019-01-17
- Granted: 2019-11-19
- Earliest claimed: 2017-07-12
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Shao Beng Law; Nicholas V. LiCausi; Errol Todd Ryan; James McMahon; Ryan S. Smith; Xunyuan Zhang
- Web page: https://patentgrep.com/patent/US10485111B2

## CPC

- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H10W 20/42: Vias, e.g. via plugs
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H05K 3/4069: {for via connections in organic insulating substrates}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/421: {Skip vias, i.e. vias that do not connect all metallization layers that they pass through}
- H10W 20/4437: {the principal metal being a transition metal}
- H05K 2201/0347: Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
- H05K 2201/09454: Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
- H05K 2201/09518: Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H10W 20/432: {comprising crossing interconnections}
- Y10T 29/49165: by forming conductive walled aperture in base
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

## Claims

### Claim 1

A method comprising:
forming a first metallization layer with a first capping layer over the first metallization layer;
forming a second metallization layer with a second capping layer over the second metallization layer;
etching through a first dielectric layer to the first capping layer;
forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping layer and depositing conductive material in an opening formed in the second metallization layer;
forming a third capping layer over the filled partial skip via and directly on the second capping layer;
forming a second dielectric layer covering select metallization features of the second metallization layer; and
forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via, wherein the third capping layer directly on the second capping layer forms a gap fill for the skip via structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the partial skip via structure is partially filled by an electroless process.

### Claim 3 (depends on 2)

The method of claim 2, wherein the electroless process comprises filling the partial skip via with Co or Ru.

### Claim 4 (depends on 1)

The method of claim 1, wherein the partial skip via structure is filled with Co or Ru by a chemical vapor deposition process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the partial skip via structure is filled with the conductive material to about 80% to 90% of its height.

### Claim 6 (depends on 1)

The method of claim 1, wherein the remaining portion of the skip via structure is filled with a metal selected from the group consisting of Co, W or Al.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a via to contact exposed metallization features of the second metallization layer in a same process as the remaining portion of the skip via structure.

### Claim 8 (depends on 7)

The method of claim 7, wherein the via and the remaining portion of the skip via structure are filled with a different material than the partial skip via structure.

### Claim 9 (depends on 8)

The method of claim 8, wherein the forming the remaining portion of the skip via structure is a self aligned process.

### Claim 10 (depends on 8)

The method of claim 8, further comprising foi wing a wiring structure in contact with the via and the remaining portion of the skip via structure using a dual damascene process.

### Claim 11 (depends on 1)

The method of claim 1, wherein the gap fill alleviates minimum insulator requirements.

### Claim 12 (depends on 11)

The method of claim 11, wherein the minimum insulator requirements are a minimum spacing between via structures.

### Claim 13 (depends on 12)

The method of claim 12, wherein the dielectric layer is a low-k dielectric material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second metallization layer is an etched metallization layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the etched metallization layer is etched using a wet process.

### Claim 16 (depends on 15)

The method of claim 15, further comprising forming a third metallization layer simultaneously with the remaining portion of the skip via structure to contact metallization features of the second metallization feature layer.