# US 10,484,718 B2 · Memory having memory cell string and coupling components > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,718 B2 - Document ID: US10484718B2 - Status: Granted - Kind: B2 - Application number: 16/197,174 - Filed: 2018-11-20 - Published: 2019-03-21 - Granted: 2019-11-19 - Earliest claimed: 2012-03-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Toru Tanzawa - Web page: https://patentgrep.com/patent/US10484718B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/35: with cell select transistors, e.g. NAND - H10W 20/43: Layouts of interconnections - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - H04N 19/117: Filters, e.g. for pre-processing or post-processing (sub-band filter banks H04N19/635) - H04N 19/14: Coding unit complexity, e.g. amount of activity or edge presence estimation (H04N19/146 takes precedence) - H04N 19/176: the region being a block, e.g. a macroblock - H04N 19/182: the unit being a pixel - H04N 19/61: in combination with predictive coding - H04N 19/80: Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation (H04N19/635, H04N19/86 take precedence) - H04N 19/82: involving filtering within a prediction loop - H04N 19/86: involving reduction of coding artifacts, e.g. of blockiness - H04N 19/865: {with detection of the former encoding block subdivision in decompressed video} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described. ## Claims ### Claim 1 A method comprising: turning on a select transistor coupled between a conductive line and a memory cell string of a device during a first time interval and a second time interval of a first operation of the device if a memory cell of the memory cell string is selected to store information in the first operation; turning on the select transistor during a portion of a first time interval of a second operation if no memory cells of the memory string are selected to store information in the second operation; and turning off the select transistor during a second time interval of the second operation if no memory cells of the memory string are selected to store information in the second operation. ### Claim 2 (depends on 1) The method of claim 1, further comprising: turning on, during the first and second time intervals of the first operation, a coupling component coupled between the select transistor and the memory cell string. ### Claim 3 (depends on 1) The method of claim 1, further comprising: turning on, during the first and second time intervals of the second operation, a coupling component coupled between the select transistor and the memory cell string. ### Claim 4 (depends on 1) The method of claim 1, further comprising: turning on, during the first and second time intervals of each of the first and second operations, a coupling component coupled between the select transistor and the memory cell string. ### Claim 5 (depends on 1) The method of claim 1, wherein: turning on the select transistor during the portion of the first time interval of the first operation includes turning on the select transistor during at least a portion of a precharge stage of the second operation; and turning off the select transistor during the second time interval of the second operation includes turning off the select transistor during a program stage of the second operation. ### Claim 6 (depends on 1) The method of claim 1, further comprising: turning off, during the first and second time intervals of the first operation, an additional select transistor coupled between the memory cell string and an additional conductive line. ### Claim 7 (depends on 1) The method of claim 1, further comprising: turning off, during the first and second time intervals of the second operation, an additional select transistor coupled between the memory cell string and an additional conductive line. ### Claim 8 (depends on 1) The method of claim 1, further comprising: turning off, during the first and second time intervals of each of the first and operations, an additional select transistor coupled between the memory cell string and an additional conductive line. ### Claim 9 A method comprising: providing a first voltage having a positive value to a gate of a select transistor coupled between a conductive line and a memory cell string of a device during a first time interval and a second time interval of a first write operation of the device if a memory cell the memory cell string is selected to store information in the first write operation; providing a second voltage having a positive value to the gate of the select transistor during a portion of the first time interval of a second write operation of the device if no memory cells of the memory string are selected to store information in the second write operation; and providing ground potential to the gate of the select transistor during a second time interval of the second write operation if no memory cells of the memory string are selected to store information in the second write operation. ### Claim 10 (depends on 9) The method of claim 9, further comprising: providing, during the first and second time intervals of the first write operation, a voltage having a positive value to a control line coupled to a coupling component, the coupling component coupled between the select transistor and the memory cell string. ### Claim 11 (depends on 9) The method of claim 9, further comprising: providing, during the first and second time intervals of the second write operation, a voltage having a positive value to the control line. ### Claim 12 (depends on 9) The method of claim 9, further comprising: providing, during the first and second time intervals of each of the first and second write operation, a voltage having a positive value to a control line coupled to a coupling component, the coupling component coupled between the select transistor and the memory cell string. ### Claim 13 (depends on 9) The method of claim 9, further comprising: providing, during the first and second time intervals of the first write operation, ground potential to an additional select transistor coupled between the memory cell string and an additional conductive line. ### Claim 14 (depends on 13) The method of claim 13, further comprising: providing a voltage having a positive value to the additional conductive during the first and second time intervals of the first write operation. ### Claim 15 (depends on 13) The method of claim 13, further comprising: providing a voltage having a positive value to the additional conductive during the first and second time intervals of the second write operation. ### Claim 16 A method comprising: providing a first voltage having a positive value to a gate of a select transistor coupled between a conductive line and a memory cell string of a device during a first time interval and a second time interval of a first write operation of the device if a memory cell the memory cell string is selected to store information in the first write operation; providing a second voltage having a positive value to the gate of the select transistor during a portion of the first time interval of a second write operation of the device if no memory cells of the memory string are selected to store information in the second write operation; providing ground potential to the gate of the select transistor during a second time interval of the second write operation if no memory cells of the memory string are selected to store information in the second write operation; and providing, during the first write operation, a voltage having a positive value to a control line coupled to a coupling component, the coupling component coupled between the select transistor and the memory cell string. ### Claim 17 (depends on 16) The method of claim 16, further comprising: providing, during the second time interval of the first write operation, an additional voltage having a positive value to the control line, wherein the positive value of the additional voltage during the second time interval of the first write operation is different from the positive value of the voltage during the first time interval of the first write operation. ### Claim 18 (depends on 17) The method of claim 17, wherein the positive value of the additional voltage during the second time interval of the first write operation is greater than the positive value of the voltage during the first time interval of the first write operation. ### Claim 19 (depends on 16) The method of claim 16, further comprising: providing, during the first and second time intervals of the first write operation, ground potential to an additional select transistor coupled between the memory cell string and an additional conductive line. ### Claim 20 (depends on 19) The method of claim 19, further comprising: providing a voltage having a positive value to the additional conductive during the first and second time intervals of the first write operation.