# US 10,484,676 B2 · Circuit and method for on-chip testing of a pixel array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,676 B2 - Document ID: US10484676B2 - Status: Granted - Kind: B2 - Application number: 14/887,390 - Filed: 2015-10-20 - Published: 2016-04-21 - Granted: 2019-11-19 - Earliest claimed: 2014-10-21 - Assignees: STMicroelectronics (Grenoble 2) SAS - Applicants: STMicroelectronics (Grenoble 2) SAS - Inventors: Richun Fei; Salvador Mir; Jocelyn Moreau - Web page: https://patentgrep.com/patent/US10484676B2 ## CPC - H04N 17/002: {for television cameras} - H04N 25/68: applied to defects - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - G01R 31/50: Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections (testing of sparking plugs H01T13/58) - H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract Testing of control wires of a pixel array of an image sensor is performed by applying a signal transition to a control wire and detecting, based on a voltage signal detected on the control wire, the duration of at least part of the signal transition on the control wire. An electrical fault in the control wire is indicated based on a comparison of the detected duration to a threshold. ## Claims ### Claim 1 A method, comprising: applying a signal to a control wire connected to control inputs of a plurality of pixels in a row of a pixel array of an image sensor; detecting, based on a change of a voltage of the applied signal on the control wire, a transition period of time over which the voltage of said applied signal on the control wire changes from a first threshold voltage to a second threshold voltage; and detecting an electrical fault in the control wire if the detected transition period of time exceeds a reference period of time. ### Claim 2 (depends on 1) The method of claim 1, wherein the electrical fault is one of a resistive open and resistive short in the control wire. ### Claim 3 (depends on 1) The method of claim 1, wherein detecting the electrical fault comprises comparing the detected transition period of time with the reference period of time. ### Claim 4 (depends on 1) The method of claim 1, wherein detecting the transition period of time comprises: asserting, by a first circuit, a first signal when the change in the voltage of the applied signal on the control wire reaches said first voltage threshold; asserting, by a second circuit, a second signal when the change in the voltage of the applied signal on the control wire reaches said second voltage threshold; and wherein the transition period of time is a difference in time between assertion of the first and second signals. ### Claim 5 A circuit, comprising: a control circuit configured to apply a signal to a control wire connected to control inputs of a plurality of pixels in a row of a pixel array of an image sensor; and a fault detection circuit coupled to the control wire and configured to: determine based on a change in voltage of the applied signal on the control wire a transition period of time over which the voltage of said applied signal on the control wire changes from a first threshold voltage to a second threshold voltage; and detect an electrical fault in the control wire if the determined transition period of time exceeds a reference period of time. ### Claim 6 (depends on 5) The circuit of claim 5, wherein the fault detection circuit comprises: a first circuit configured to assert a first signal when the change in the voltage of the applied signal on the control wire reaches said first voltage threshold; and a second circuit configured to assert a second signal when the change in the voltage of the applied signal on the control wire reaches said second voltage threshold; wherein the transition period of time is a time difference between assertion of the first and second signals. ### Claim 7 (depends on 6) The circuit of claim 6, wherein the first circuit comprises a low threshold inverter having an input coupled to the control wire. ### Claim 8 (depends on 6) The circuit of claim 6, wherein the second circuit comprises a half Schmitt trigger having an input coupled to the control wire. ### Claim 9 (depends on 6) The circuit of claim 6, wherein: the first circuit comprises a first transistor having its control node coupled to the control wire; and the second circuit comprises second and third transistors each having its control node coupled to the control wire. ### Claim 10 (depends on 9) The circuit of claim 9, wherein the first transistor has a width/length ratio greater than that of each of the second and third transistors. ### Claim 11 (depends on 9) The circuit of claim 9, wherein the second circuit further comprises: a fourth transistor coupled in series with the second and third transistors; and a fifth transistor coupled by its main conducting nodes between a supply voltage node and an intermediate node between the second and third transistors, a control node of the fifth transistor being coupled to an intermediate node between the second and fourth transistors. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the fourth transistor has its control node coupled to a reset signal, and wherein the first circuit comprises a sixth transistor coupled to one of the main conducting nodes of the first transistor and having its control node coupled to the reset signal. ### Claim 13 (depends on 5) The circuit of claim 5, wherein the reference period of time is generated by a buffer receiving the second signal. ### Claim 14 A system, comprising: a plurality of testing circuits, each testing circuit coupled to a corresponding one of a plurality of control wires, wherein each testing circuit comprises: a control circuit configured to apply a signal to a control wire connected to control inputs of a plurality of pixels in a row of a pixel array of an image sensor; and a fault detection circuit coupled to the control wire and configured to: determine based on a change in voltage of the applied signal on the control wire a time duration over which the voltage of said applied signal on the control wire changes from a first threshold voltage to a second threshold voltage; and detect an electrical fault in the control wire if the determined time duration exceeds a reference time duration; and a plurality of synchronous devices configured to store information indicating the detected electrical fault, wherein the synchronous devices are daisy-chained together for serial output of the stored information for each of the plurality of control wires. ### Claim 15 (depends on 14) The system of claim 14, wherein each fault detection circuit comprises: a first circuit configured to assert a first signal when the change in the voltage of the applied signal on the control wire reaches said first voltage threshold; and a second circuit configured to assert a second signal when the change in the voltage of the applied signal on the control wire reaches said second voltage threshold; wherein the time duration is a time difference between assertion of the first and second signals. ### Claim 16 (depends on 15) The system of claim 15, further comprising: first and second bit lines; a first transistor coupled between the first bit line and a ground voltage node and receiving at its control node the first signal output from the fault detection circuit of a first testing circuit of said plurality of testing circuits; and a second transistor coupled between the second bit line and the ground voltage node and receiving at its control node the second signal output from the fault detection circuit of the first testing circuit of said plurality of testing circuits. ### Claim 17 (depends on 16) The system of claim 16, further comprising: a third transistor coupled between the first bit line and the ground voltage node and receiving at its control node the first signal output from the fault detection circuit of a second testing circuit of said plurality of testing circuits; and a fourth transistor coupled between the second bit line and the ground voltage node and receiving at its control node the second signal output from the fault detection circuit of the second testing circuit of said plurality of testing circuits. ### Claim 18 (depends on 15) The system of claim 15, wherein: the first circuit comprises a first test transistor having its control node coupled to the control wire; and the second circuit comprises second and third test transistors each having its control node coupled to the control wire. ### Claim 19 (depends on 18) The system of claim 18, wherein the first test transistor has a width/length ratio greater than that of each of the second and third test transistors. ### Claim 20 (depends on 18) The system of claim 18, wherein the second circuit further comprises: a fourth test transistor coupled in series with the second and third test transistors; and a fifth test transistor coupled by its main conducting nodes between a supply voltage node and an intermediate node between the second and third test transistors, a control node of the fifth test transistor being coupled to an intermediate node between the second and fourth test transistors. ### Claim 21 (depends on 20) The system of claim 20, wherein the fourth test transistor has its control node coupled to a reset signal, and wherein the first circuit comprises a sixth test transistor coupled to one of the main conducting nodes of the first test transistor and having its control node coupled to the reset signal. ### Claim 22 (depends on 14) The system of claim 14, wherein the reference time duration is generated by a buffer receiving the second signal.