# US 10,484,655 B2 · Gate driving circuit and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,655 B2 - Document ID: US10484655B2 - Status: Granted - Kind: B2 - Application number: 15/327,301 - Filed: 2016-12-30 - Published: 2018-11-22 - Granted: 2019-11-19 - Earliest claimed: 2016-12-27 - Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd. - Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd. - Inventors: Yafeng Li - Web page: https://patentgrep.com/patent/US10484655B2 ## CPC - H04N 9/30: using solid-state colour display devices - G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)} - G09G 3/3677: {suitable for active matrices only} - G09G 2310/0264: Details of driving circuits - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Disclosed is a gate driving circuit and a display device, which solve the technical problem that the prior art is easy to cause abnormal output of gate driving signals. The gate driving circuit includes a precharge unit circuit, an output unit circuit, and a holding unit circuit. The output unit circuit includes a first reference point and a clock signal line. The holding unit circuit includes a second reference point and a holding signal line, and a holding capacitor is connected between the second reference point and the holding signal line. ## Claims ### Claim 1 A gate driving circuit, comprising a precharge unit circuit, an output unit circuit, and a holding unit circuit, wherein: the output unit circuit comprises a first reference point and a clock signal line; the holding unit circuit comprises a second reference point and a holding signal line, and a holding capacitor is connected between the second reference point and the holding signal line; before an output period, the precharge unit circuit outputs a high level to the first reference point; during the output period, the first reference point is maintained at a high level, and the clock signal line outputs a high level to cause the output unit circuit to output a scanning signal to a scan line; after the output period, the holding signal line outputs a periodic high level to the second reference point through the holding capacitor, so that the first reference point is maintained at a low level; wherein the holding unit circuit further comprises a low-level signal line, a fourth switch tube, and a second capacitor, wherein a gate of the fourth switch tube is connected to the second reference point, a source thereof is connected to the low-level signal line, and a drain thereof is connected to the scan line; and wherein the second capacitor is connected between the second reference point and the low-level signal line. ### Claim 2 (depends on 1) The gate driving circuit according to claim 1, wherein, the precharge unit circuit comprises a first switch tube and a high-level signal line, wherein a gate of the first switch tube is connected to a previous-stage scan line, a source thereof is connected to the high-level signal line, and a drain thereof is connected to the first reference point. ### Claim 3 (depends on 2) The gate driving circuit according to claim 2, wherein, the precharge unit circuit further comprises a second switch tube, wherein a gate of the second switch tube is connected to a next-stage scan line, a source thereof is connected to the high-level signal line, and a drain thereof is connected to the first reference point. ### Claim 4 (depends on 1) The gate driving circuit according to claim 1, wherein, the output unit circuit also comprises a third switch tube and a first capacitor, wherein a gate of the third switch tube is connected to the first reference point, a source thereof is connected to the clock signal line, and a drain thereof is connected to a current-stage scan line; and wherein the first capacitor is connected between the gate and the drain of the third switch tube. ### Claim 5 (depends on 1) The gate driving circuit according to claim 1, wherein the holding unit circuit further comprises a fifth switch tube, wherein a gate of the fifth switch tube is connected to the second reference point, a source thereof is connected to the first reference point, and a drain thereof is connected to the low-level signal line. ### Claim 6 (depends on 5) The gate driving circuit according to claim 5, wherein the holding unit circuit further comprises a sixth switch tube, wherein a gate of the sixth switch tube is connected to the first reference point, a source thereof is connected to the second reference point, and a drain thereof is connected to the low-level signal line. ### Claim 7 (depends on 1) The gate driving circuit according to claim 1, wherein, a duty cycle of the periodic high level outputted by the holding signal line is 25% or 50%. ### Claim 8 A display device, comprising a plurality of cascaded gate driving circuits each of which comprises a precharge unit circuit, an output unit circuit, and a holding unit circuit, wherein: the output unit circuit comprises a first reference point and a clock signal line; the holding unit circuit comprises a second reference point and a holding signal line, and a holding capacitor is connected between the second reference point and the holding signal line; before an output period, the precharge unit circuit outputs a high level to the first reference point; during the output period, the first reference point is maintained at a high level, and the clock signal line outputs a high level to cause the output unit circuit to output a scanning signal to a scan line; after the output period, the holding signal line outputs a periodic high level to the second reference point through the holding capacitor, so that the first reference point is maintained at a low level; where the holding unit circuit further comprises a low-level signal line, a fourth switch tube, and a second capacitor, wherein a gate of the fourth switch tube is connected to the second reference point, a source thereof is connected to the low-level signal line, and a drain thereof is connected to the scan line; and wherein the second capacitor is connected between the second reference point and the low-level signal line. ### Claim 9 (depends on 8) The display device according to claim 8, wherein, the precharge unit circuit comprises a first switch tube and a high-level signal line, wherein a gate of the first switch tube is connected to a previous-stage scan line, a source thereof is connected to the high-level signal line, a drain thereof is connected to the first reference point. ### Claim 10 (depends on 9) The display device according to claim 9, wherein, the precharge unit circuit further comprises a second switch tube, wherein a gate of the second switch tube is connected to a next-stage scan line, a source thereof is connected to the high-level signal line, and a drain thereof is connected to the first reference point. ### Claim 11 (depends on 8) The display device according to claim 8, wherein, the output unit circuit further comprises a third switch tube and a first capacitor, wherein a gate of the third switch tube is connected to the first reference point, a source thereof is connected to the clock signal line, and a drain thereof is connected to the current-stage scan line; and wherein the first capacitor is connected between the gate and the drain of the third switch tube. ### Claim 12 (depends on 8) The display device according to claim 8, wherein the holding unit circuit further comprises a fifth switch tube, wherein a gate of the fifth switch tube is connected to the second reference point, a source thereof is connected to the first reference point, and a drain thereof is connected to the low-level signal line. ### Claim 13 (depends on 12) The display device according to claim 12, wherein, wherein the holding unit circuit further comprises a sixth switch tube, wherein a gate of the sixth switch tube is connected to the first reference point, a source thereof is connected to the second reference point, and a drain thereof is connected to the low-level signal line. ### Claim 14 (depends on 8) The display device according to claim 8, wherein, a duty cycle of the periodic high level outputted by the holding signal line is 25% or 50%. ### Claim 15 (depends on 8) The display device according to claim 8, wherein, the display device comprises an array substrate, and the gate driving circuit is formed on the array substrate.