# US 10,484,635 B2 · Synchronous time code image sensor

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- Number: US 10,484,635 B2
- Document ID: US10484635B2
- Status: Granted
- Kind: B2
- Application number: 15/675,762
- Filed: 2017-08-13
- Published: 2018-05-03
- Granted: 2019-11-19
- Earliest claimed: 2016-11-03
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Applicants: Commissariat à l'Energie Atomique et aux Energies Alternatives
- Inventors: Arnaud Verdant; William Guicquero
- Web page: https://patentgrep.com/patent/US10484635B2

## CPC

- H04N 25/767: Horizontal readout lines, multiplexers or registers
- H04N 25/583: with different integration times
- H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

An image sensor including: a plurality of pixels, each pixel being capable of supplying an output signal representative of a quantity of light energy received from a time of beginning of a pixel integration phase; and a control circuit configured to, during a phase of acquisition of an image, successively select each pixel a number n of times during a same pixel integration phase, without resetting the pixel between the first and the last selection of the pixel and, for each selection of a pixel, compare the output signal of the pixel with a quantization threshold and read a binary signal representative of the result of the comparison.

## Claims

### Claim 1

An image sensor comprising:
a plurality of pixels, each pixel comprising a photodiode and a sense node and being capable of supplying on the sense node an output signal representative of a quantity of light energy received by its photodiode during a pixel integration phase; and
a control circuit configured to, during a phase of acquisition of an image, successively select each pixel a number n of times without resetting the pixel between the first and the last selection of the pixel and, for each selection of a pixel, compare the output signal of the pixel with a quantization threshold and read a binary signal representative of the result of the comparison, a sequence of n binary samples thus obtained forming a pixel output value.

### Claim 2 (depends on 1)

The sensor of claim 1, wherein, for each pixel, the n successive selections of the pixel are performed during a same pixel integration phase.

### Claim 3 (depends on 2)

The sensor of claim 2, wherein the quantization threshold is constant all along the integration phase.

### Claim 4 (depends on 2)

The sensor of claim 2, wherein the control circuit is configured so that a time interval between two successive selections of the pixel is substantially constant all along the pixel integration phase.

### Claim 5 (depends on 2)

The sensor of claim 2, wherein the control circuit is configured so that a time interval between two successive selections of the pixel varies during the pixel integration phase.

### Claim 6 (depends on 5)

The sensor of claim 5, wherein the control circuit is configured so that the time interval between two successive selections of the pixel is inversely proportional to a rank of the selection from among the n successive selections of the pixel of the integration phase.

### Claim 7 (depends on 1)

The sensor of claim 1, wherein, for each pixel, the n successive selections of the pixel are performed during a readout phase following the pixel integration phase.

### Claim 8 (depends on 7)

The sensor of claim 7, wherein the quantization threshold varies monotonously all along the readout phase.

### Claim 9 (depends on 1)

The sensor of claim 1, wherein each pixel comprises:
a reset transistor coupling the sense node to a pixel reset node;
a readout transistor assembled as a follower source, having a gate connected to the sense node and having a drain connected to the reset node; and
a selection transistor coupling a source of the readout transistor to an output conductive track of the pixel.

### Claim 10 (depends on 9)

The sensor of claim 9, wherein the control circuit is configured to, during the image acquisition phase, implement, for each pixel, a pixel initialization phase comprising resetting the sense node of the pixel to a first reference voltage via the output conductive track, the selection transistor, the readout transistor, and the reset transistor of the pixel.

### Claim 11 (depends on 10)

The sensor of claim 10, wherein the control circuit is configured to, during the initialization phase of the pixel, configure the pixel as a common-source amplifier by applying a bias current to the pixel reset node and by applying a fixed reference potential to the output conductive track of the pixel.

### Claim 12 (depends on 10)

The sensor of claim 10, wherein the control circuit is configured to, during the phase of initialization of the pixel, implement the successive steps of:
setting to a reference potential the output conductive track of the pixel and then setting to a high impedance state said output conductive track;
controlling the reset transistor and the selection transistor to the on state; and
setting to a high impedance state the pixel reset node and forcing the output conductive track of the pixel to the reference potential.

### Claim 13 (depends on 9)

The sensor of claim 9, wherein each pixel further comprises a transfer gate capable of controlling the transfer of photogenerated charges between the photodiode and the sense node.

### Claim 14 (depends on 9)

The sensor of claim 9, wherein the control circuit comprises a peripheral readout circuit comprising at least one comparator, and wherein the output conductive track of each pixel is connected to a first input of said at least one comparator.

### Claim 15 (depends on 14)

The sensor of claim 14, wherein the control circuit is configured to, for each selection of the pixel during the integration phase of the pixel, implement the steps of:
a) precharging the output conductive track of the pixel to a second reference voltage;
b) applying a third reference voltage greater than the second reference voltage to a second input of said at least one comparator;
c) turning on the pixel selection transistor; and
d) after a predetermined settling time after step c), reading an output value of the comparator.

### Claim 16 (depends on 1)

The sensor of claim 1, wherein the pixels are arranged in an array of rows and columns, and wherein the control circuit is capable of simultaneously controlling the pixels of a same row and of successively controlling the pixels of different rows according to a control method of rolling shutter type.

### Claim 17 (depends on 1)

The sensor of claim 1, wherein said quantization threshold is adjustable.

### Claim 18 (depends on 1)

A device comprising the sensor of claim 1, and a circuit of on-the-fly processing of the binary signals read by the control circuit.

### Claim 19 (depends on 18)

The device of claim 18, wherein the processing circuit is capable, for each scanning of all the plurality of pixels, of multiplying a binary input vector formed by all binary signals read by the control circuit of the sensor for the plurality of pixels, by a transformation matrix.

### Claim 20 (depends on 19)

The device of claim 19, wherein the processing circuit is capable, during successive scannings of all the plurality of pixels, of integrating successive output vectors resulting from the multiplication of the successive input vectors by the transformation matrix.