# US 10,484,624 B2 · Imaging sensors with per-pixel control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,624 B2 - Document ID: US10484624B2 - Status: Granted - Kind: B2 - Application number: 15/644,957 - Filed: 2017-07-10 - Published: 2019-01-10 - Granted: 2019-11-19 - Earliest claimed: 2017-07-10 - Assignees: Semiconductor Components Industries, LLC - Applicants: Semiconductor Components Industries, LLC - Inventors: Tomas Geurts - Web page: https://patentgrep.com/patent/US10484624B2 ## CPC - H04N 25/443: by reading pixels from selected two-dimensional [2D] regions of the array, e.g. for windowing or digital zooming - H04N 25/531: by controlling rolling shutters in CMOS SSIS - H04N 25/532: by controlling global shutters in CMOS SSIS - H04N 25/535: by dynamic region selection - H04N 25/583: with different integration times - H04N 25/59: by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance - H04N 25/622: {by controlling anti-blooming drains} - H04N 25/771: comprising storage means other than floating diffusion - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract Image sensors may include pixel circuitry to enable per-pixel integration time and read-out control. Two transistors may be coupled in series for per-pixel control, with one of the transistors being controlled on a row-by-row basis and the other transistor being controlled on a column-by-column basis. The two transistors in series may be coupled directly to each other without any intervening structures. Two transistors in series between a photodiode and a power supply terminal enables per-pixel control of starting an integration time, two transistors in series between a photodiode and a charge storage region enables per-pixel control of ending an integration time, and two transistors in series between a charge storage region and a floating diffusion region enables per-pixel control of read-out. ## Claims ### Claim 1 An image sensor comprising an array of imaging pixels, wherein each imaging pixel comprises: a photodiode; a floating diffusion region; a charge storage region interposed between the photodiode and the floating diffusion region; first and second transistors interposed between the photodiode and the charge storage region, wherein the first transistor has a gate that receives a horizontal transfer control signal and wherein the second transistor has a gate that receives a vertical transfer control signal; and third and fourth transistors interposed between the charge storage region and the floating diffusion region, wherein the third transistor has a gate that receives an additional horizontal transfer control signal and the fourth transistor has a gate that receives an additional vertical transfer control signal. ### Claim 2 (depends on 1) The image sensor defined in claim 1, wherein charge is transferred from the photodiode to the charge storage region only when both the first and second transistors are asserted. ### Claim 3 (depends on 1) The image sensor defined in claim 1, wherein the image sensor has a first column of imaging pixels and a first row of imaging pixels, wherein the second transistor of each imaging pixel in the first column receives the same vertical transfer control signal, and wherein the first transistor of each imaging pixel in the first row receives the same horizontal transfer control signal. ### Claim 4 (depends on 1) The image sensor defined in claim 1, wherein charge is transferred from the charge storage region to the floating diffusion region only when both the third and fourth transistors are asserted. ### Claim 5 (depends on 1) The image sensor defined in claim 1, wherein each imaging pixel further comprises: a power supply terminal; and fifth and sixth transistors interposed between the photodiode and the power supply terminal. ### Claim 6 (depends on 5) The image sensor defined in claim 5, wherein the photodiode is coupled to the power supply terminal when the fifth and sixth transistors are asserted. ### Claim 7 (depends on 1) The image sensor defined in claim 1, wherein each imaging pixel further comprises: a power supply terminal; and a fifth transistor coupled between the power supply terminal and a node that is interposed between the first and second transistors. ### Claim 8 (depends on 7) The image sensor defined in claim 7, wherein the photodiode is coupled to the power supply terminal when the first and fifth transistors are asserted. ### Claim 9 An image sensor comprising an array of imaging pixels, wherein each imaging pixel comprises: a photodiode; a floating diffusion region; and first and second transistors interposed between the photodiode and the floating diffusion region, wherein the first transistor is coupled directly to the second transistor without any intervening structures, wherein the first transistor of each imaging pixel has a gate that receives a horizontal transfer control signal and wherein the second transistor of each imaging pixel has a gate that receives a vertical transfer control signal; and a third transistor coupled between a power supply terminal and a node that is interposed between the first and second transistors. ### Claim 10 (depends on 9) The image sensor defined in claim 9, wherein charge is transferred from the photodiode to the floating diffusion region only when both the first and second transistors are asserted. ### Claim 11 (depends on 9) The image sensor defined in claim 9, wherein the image sensor has a first column of imaging pixels and a first row of imaging pixels, wherein the second transistor of each imaging pixel in the first column receives the same vertical transfer signal, and wherein the first transistor of each imaging pixel in the first row receives the same horizontal transfer signal. ### Claim 12 (depends on 9) The image sensor defined in claim 9, wherein the photodiode is coupled to the power supply terminal when the first and third transistors are asserted. ### Claim 13 An image sensor comprising an array of imaging pixels arranged in rows and columns, wherein each imaging pixel is positioned in a respective row and a respective column and wherein each imaging pixel comprises: a photodiode; a charge storage region; a floating diffusion region; first and second transistors interposed between the photodiode and the charge storage region, wherein the first transistor of each imaging pixel has a gate that receives a horizontal transfer control signal associated with the respective row of the imaging pixel and wherein the second transistor of each imaging pixel has a gate that receives a vertical transfer control signal associated with the respective column of the imaging pixel; and third and fourth transistors interposed between the charge storage region and the floating diffusion region, wherein the third transistor of each imaging pixel has a gate that receives an additional horizontal transfer control signal associated with the respective row of the imaging pixel and wherein the fourth transistor of each imaging pixel has a gate that receives an additional vertical transfer control signal associated with the respective column of the imaging pixel. ### Claim 14 (depends on 13) The image sensor defined in claim 13, wherein each imaging pixel further comprises: a power supply terminal; and fifth and sixth transistors interposed between the photodiode and the power supply terminal, wherein the fifth transistor of each imaging pixel has a gate that receives a horizontal anti-blooming control signal associated with the respective row of the imaging pixel and wherein the sixth transistor of each imaging pixel has a gate that receives a vertical anti-blooming control signal associated with the respective column of the imaging pixel. ### Claim 15 (depends on 13) The image sensor defined in claim 13, wherein each imaging pixel further comprises: a power supply terminal; and a fifth transistor coupled between the power supply terminal and a node that is interposed between the first and second transistors, wherein the fifth transistor of each imaging pixel has a gate that receives an anti-blooming control signal associated with the respective column of the imaging pixel.