# US 10,484,578 B2 · Synchronizing video outputs towards a single display frequency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,578 B2 - Document ID: US10484578B2 - Status: Granted - Kind: B2 - Application number: 15/941,929 - Filed: 2018-03-30 - Published: 2019-10-03 - Granted: 2019-11-19 - Earliest claimed: 2018-03-30 - Assignees: CAE Inc. - Applicants: CAE Inc. - Inventors: Samuel Berube; Jean-Sébastien Dion - Web page: https://patentgrep.com/patent/US10484578B2 ## CPC - H04N 5/067: Arrangements or circuits at the transmitter end - G06F 3/1438: {using more than one graphics controller} - G06F 3/1446: {display composed of modules, e.g. video walls} - G09G 5/12: Synchronisation between the display unit and other units, e.g. other display units, video-disc players - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - G09G 2300/026: Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G 2360/06: Use of more than one graphics processor to process data before displaying to one or more screens - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Method and system for synchronizing video output towards a single display frequency comprising providing a shared reference signal for synchronizing, at the single display frequency, video output between two or more image generator processors each driving at least one independent video card. Each of the video cards supports on-the-fly image refresh rate adaptation based on responsiveness from the corresponding image generator processor. The method also comprises, at each one of the image generator processors, artificially affecting, in real-time, image generation rendering speed during a next frame generation processing to trigger the on-the-fly image refresh rate adaptation by the one image generator processor's video card for proactively scheduling refresh of an image corresponding to the next frame by the one image generator processor's video card, thereby aligning the refresh of the image to the shared reference signal while avoiding manipulation of video card's memory registers by the one image generator processor. ## Claims ### Claim 1 A method for synchronizing video output towards a single display frequency comprising: providing a shared reference signal for synchronizing, at the single display frequency, video output between two or more image generator processors each driving at least one independent video card, wherein each of the independent video cards supports on-the-fly image refresh rate adaptation based on responsiveness from the corresponding image generator processor; and at each one of the image generator processors, artificially affecting, in real-time, image generation rendering speed during a next frame generation processing to trigger the on-the-fly image refresh rate adaptation by the one image generator processor's video card for proactively scheduling refresh of an image corresponding to the next frame by the one image generator processor's video card, thereby aligning the refresh of the image to the shared reference signal while avoiding manipulation of memory registers of the one image generator processor's video card by the one image generator processor. ### Claim 2 (depends on 1) The method for synchronizing video output of claim 1, wherein artificially affecting, in real-time, image generation rendering speed is performed by programmatically mimicking, in real-time, image generation rendering lag during the next frame generation processing. ### Claim 3 (depends on 1) The method for synchronizing video output of claim 1, wherein artificially affecting, in real-time, image generation rendering speed is performed by programmatically mimicking, in real-time, image generation rendering hastening during the next frame generation processing. ### Claim 4 (depends on 1) The method for synchronizing video output of claim 1, wherein, when the one image generator processor is a master image generator processor, artificially affecting, in real-time, image generation rendering speed involves scheduling the next frame generation processing by a predetermined target timer linked to the shared reference signal while avoiding manipulation of the video card's memory registers by the master image generator processor. ### Claim 5 (depends on 1) The method for synchronizing video output of claim 1, wherein, when the one image generator processor is a slave image generator processor and unless the shared reference signal is aligned to a local slave signal, artificially affecting, in real-time, image generation rendering speed involves scheduling the next frame generation processing by varying a mimicked rendering timer in real-time during a next slave frame processing to trigger the on-the-fly image refresh rate adaptation by the slave image generator processor's video card for reducing a time distance between the shared reference and the local slave signal, thereby improving synchronicity of an image corresponding to the next slave frame and an image corresponding to another next frame from another of the two or more image generator processors while avoiding manipulation of the video card's memory registers by the slave image generator processor. ### Claim 6 (depends on 5) The method for synchronizing video output of claim 5, further comprising sending, from the slave image generator processor towards a reference signal generator, an indication of the time distance between the slave local signal and the shared reference signal. ### Claim 7 (depends on 6) The method for synchronizing video output of claim 6, wherein the indication comprises the time distance between the shared reference and the local slave reference signal. ### Claim 8 (depends on 6) The method for synchronizing video output of claim 6, wherein the reference signal generator is provided by a master image generator processor from the two or more image generator processors. ### Claim 9 (depends on 6) The method for synchronizing video output of claim 6, further comprising updating the shared reference signal by adjusting the predetermined target timer at the reference signal generator considering a plurality of received indications comprising the received indication of the time distance between the slave local signal and the shared reference signal. ### Claim 10 (depends on 9) The method for synchronizing video output of claim 9, wherein adjusting the predetermined target timer is performed by subtracting a minimum value from a plurality of received time distances from the plurality of received indications. ### Claim 11 (depends on 5) The method for synchronizing video output of claim 5, wherein when the one image generator processor is the slave image generator processor and when the shared reference signal is aligned with the local slave reference signal, processing the next frame without modifying the mimicked rendering timer. ### Claim 12 (depends on 2) The method of claim 2 further comprising, independently from each of the two or more image generator processors, providing each of the images corresponding to each of the next frame at the single display frequency. ### Claim 13 A system comprising: a display system for displaying a synchronized composite image thereon at a single display frequency; a plurality of independent video cards each configured for supporting on-the-fly image refresh rate adaptation based on responsiveness from a corresponding image generator process; and a plurality of image generator processors each configured for driving one or more of the plurality of independent video cards and having access to a shared reference signal; wherein each one of the plurality of image generator processors is configured for artificially affecting, in real-time, image generation rendering speed during a next frame generation processing to trigger the on-the-fly image refresh rate adaptation by the one image generator processor's video card for proactively scheduling refresh of an image corresponding to the next frame by the one image generator processor's video card, thereby aligning the refresh of the image to the shared reference signal while avoiding manipulation of memory registers of the one image generator processor's video card by the one image generator processor; wherein the composite image comprises each of the images corresponding to the next frames from each one of the plurality of image generator processors. ### Claim 14 (depends on 13) The system of claim 13, wherein the one image generator processor is configured for artificially affecting, in real-time, image generation rendering speed by programmatically mimicking, in real-time, image generation rendering lag during the next frame generation processing. ### Claim 15 (depends on 13) The system of claim 13, wherein the one image generator processor is configured for artificially affecting, in real-time, image generation rendering speed by programmatically mimicking, in real-time, image generation rendering hastening during the next frame generation processing. ### Claim 16 (depends on 13) The system of claim 13, wherein the plurality of image generator processors comprise a master image generator processor and one or more slave image generator processor and, when the one image generator processor is the master image generator processor, the master image generator processor is configured for artificially affecting, in real-time, image generation rendering speed during the next frame generation processing by scheduling a next master frame generation processing by a predetermined target timer linked to the shared reference signal while avoiding manipulation of the video card's memory registers by the master image generator processor. ### Claim 17 (depends on 13) The system of claim 13, wherein the plurality of image generator processors comprise one or more slave image generator processor and, when the one image generator processor is the slave image generator processor and unless the shared reference signal is aligned to a local slave signal, the slave image generator processor is configured for artificially affecting, in real-time, image generation rendering speed during the next frame generation processing by varying a mimicked rendering timer in real-time during a next slave frame processing to trigger the on-the-fly image refresh rate adaptation by the slave image generator processor's video card for reducing a time distance between the shared reference and the local slave signal, thereby improving synchronicity of an image corresponding to the next slave frame and an image corresponding to another next frame from another of the plurality of image generator processors while avoiding manipulation of the video card's memory registers by the slave image generator processor. ### Claim 18 (depends on 17) The system of claim 17, wherein the slave image generator processor is further configured for sending, towards a reference signal generator, an indication of the time distance between the slave local signal and the shared reference signal. ### Claim 19 (depends on 18) The system of claim 18, wherein the indication comprises the time distance between the shared reference and the local slave reference signal. ### Claim 20 (depends on 18) The system of claim 18, wherein the reference signal generator is configured to update the shared reference signal by adjusting the predetermined target timer considering a plurality of received indications comprising the received indication of the time distance between the slave local signal and the shared reference signal.