# US 10,484,577 B1 · Real-time interleaved multi-scan-out

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- Number: US 10,484,577 B1
- Document ID: US10484577B1
- Status: Granted
- Kind: B1
- Application number: 15/677,972
- Filed: 2017-08-15
- Granted: 2019-11-19
- Earliest claimed: 2017-08-15
- Assignees: Facebook Technologies, LLC
- Applicants: Facebook Technologies, LLC
- Inventors: Rui Zhang
- Web page: https://patentgrep.com/patent/US10484577B1

## CPC

- G02B 27/0176: {characterised by mechanical features}
- G02B 27/0172: {characterised by optical features}
- G09G 3/003: {to produce spatial visual effects}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/22: using controlled light sources
- G09G 2310/0205: Simultaneous scanning of several lines in flat panels
- G09G 2310/021: Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
- G09G 2310/0221: with use of split matrices (G09G3/3644 and G09G3/3666 take precedence)
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Disclosed herein are techniques for single-panel image display. A display device comprises a two-dimensional pixel array and a control circuit. The two-dimensional pixel array comprises a first region and a second region, each region including two or more lines of pixels. The control circuit is configured to select a first set of one or more lines of pixels in the first region to receive image data for an image frame, and, before selecting a second set of one or more lines of pixels in the first region to receive image data for the same image frame, select a first set of one or more lines of pixels in the second region to receive image data for the same image frame.

## Claims

### Claim 1

A display device comprising:
a two-dimensional pixel array comprising a first region and a second region, each region including two or more lines of pixels; and
a control circuit configured to:
select a first one or more lines of pixels in the first region to receive image data for an image frame; and
select, after selecting the first one or more lines of pixels in the first region and before selecting a second one or more lines of pixels in the first region to receive the image data for the image frame, a first one or more lines of pixels in the second region to receive the image data for the image frame.

### Claim 2 (depends on 1)

The display device of claim 1, wherein:
the first one or more lines of pixels in the first region consists of a single line of pixels; and
the first one or more lines of pixels in the second region consists of a single line of pixels.

### Claim 3 (depends on 1)

The display device of claim 1, wherein:
the first region of the two-dimensional pixel array is configured to display images to one eye of a user; and
the second region of the two-dimensional pixel array is configured to display images to another eye of the user.

### Claim 4 (depends on 1)

The display device of claim 1, wherein the control circuit comprises a first group of gates and a second group of gates, wherein:
each gate comprises:
a clock input;
a trigger input; and
an output coupled to a respective line of pixels in the first region or the second region;
the outputs of the first group of gates are coupled to the two or more lines of pixels in the first region; and
the outputs of the second group of gates are coupled to the two or more lines of pixels in the second region.

### Claim 5 (depends on 4)

The display device of claim 4, wherein:
the clock inputs of the first group of gates are coupled to a first clock line; and
the clock inputs of the second group of gates are coupled to a second clock line.

### Claim 6 (depends on 4)

The display device of claim 4, wherein:
in the first group of gates,
the trigger input of a first gate in the first group of gates is coupled to a first trigger line for receiving a first trigger signal; and
the output of each gate other than a last gate in the first group of gates is coupled to the trigger input of a next gate in the first group of gates; and
in the second group of gates,
the trigger input of a first gate in the second group of gates is coupled to a second trigger line for receiving a second trigger signal; and
the output of each gate other than a last gate in the second group of gates is coupled to the trigger input of a next gate in the second group of gates.

### Claim 7 (depends on 6)

The display device of claim 6, wherein:
the first trigger signal includes a first pulse;
the second trigger signal includes a second pulse; and
the second pulse is later than the first pulse.

### Claim 8 (depends on 6)

The display device of claim 6, wherein:
the trigger input of the first gate in the second group of gates is coupled to the second trigger line through a switch, the switch configured to selectively couple the trigger input of the first gate in the second group of gates to the second trigger line or to the output of the last gate in the first group of gates.

### Claim 9 (depends on 6)

The display device of claim 6, further comprising a driver circuit configured to provide:
the first trigger signal;
the second trigger signal; and
one or more clock signals for driving the clock inputs of the first group of gates and the clock inputs of the second group of gates.

### Claim 10 (depends on 9)

The display device of claim 9, wherein the driver circuit is further configured to concurrently provide the image data to pixels in a line of pixels of the first one or more lines of pixels in the first region.

### Claim 11 (depends on 10)

The display device of claim 10, wherein the driver circuit is further configured to provide scrambled image data for an image frame to the two-dimensional pixel array.

### Claim 12 (depends on 9)

The display device of claim 9, wherein the driver circuit is further configured to provide a backlight control signal for the two-dimensional pixel array.

### Claim 13

A control circuit for a two-dimensional pixel array, the control circuit comprising:
a first group of gates; and
a second group of gates,
wherein the two-dimensional pixel array comprises a first region and a second region, each region including two or more lines of pixels; and
wherein the control circuit is configured to:
select, using the first group of gates, a first one or more lines of pixels in the first region to receive image data for an image frame; and
select, using the second group of gates, a first one or more lines of pixels in the second region to receive the image data for the image frame, after selecting the first one or more lines of pixels in the first region and before selecting a second one or more lines of pixels in the first region using the first group of gates to receive the image data for the image frame.

### Claim 14 (depends on 13)

The control circuit of claim 13, wherein each gate in the first group of gates and the second group of gates comprises:
a clock input;
a trigger input; and
an output coupled to a respective line of pixels in the first region or the second region.

### Claim 15 (depends on 14)

The control circuit of claim 14, wherein:
in the first group of gates,
the trigger input of a first gate in the first group of gates is coupled to a first trigger line for receiving a first trigger signal; and
the output of each gate other than a last gate in the first group of gates is coupled to the trigger input of a next gate in the first group of gates; and
in the second group of gates,
the trigger input of a first gate in the second group of gates is coupled to a second trigger line for receiving a second trigger signal; and
the output of each gate other than a last gate in the second group of gates is coupled to the trigger input of a next gate in the second group of gates.

### Claim 16 (depends on 15)

The control circuit of claim 15, wherein:
the trigger input of the first gate in the second group of gates is coupled to the second trigger line through a switch; and
the switch is configured to selectively couple the trigger input of the first gate in the second group of gates to the second trigger line or the output of the last gate in the first group of gates.

### Claim 17

A method for single-panel image display, the method comprising:
selecting, from a two-dimensional pixel array that comprises a first region and a second region each comprising two or more lines of pixels, a first one or more lines of pixels in the first region to receive image data for an image frame; and
selecting, after selecting the first one or more lines of pixels in the first region and before selecting a second one or more lines of pixels in the first region to receive the image data for the image frame, a first one or more lines of pixels in the second region to receive the image data for the image frame.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
selecting the first one or more lines of pixels in the first region includes selecting two or more lines of pixels in the first region; and
selecting the first one or more lines of pixels in the second region includes selecting two or more lines of pixels in the second region.

### Claim 19 (depends on 17)

The method of claim 17, wherein:
selecting the first one or more lines of pixels in the first region includes selecting the first one or more lines of pixels in the first region using a first trigger signal; and
selecting the first one or more lines of pixels in the second region includes selecting the first one or more lines of pixels in the second region using a second trigger signal, wherein a phase of the second trigger signal is different from a phase of the first trigger signal.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
providing, concurrently, the image data to pixels in a line of pixels of the first one or more lines of pixels in the first region.
