# US 10,484,167 B2 · Circuit for and method of receiving a signal in an integrated circuit device

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- Number: US 10,484,167 B2
- Document ID: US10484167B2
- Status: Granted
- Kind: B2
- Application number: 15/920,251
- Filed: 2018-03-13
- Published: 2019-09-19
- Granted: 2019-11-19
- Earliest claimed: 2018-03-13
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Yi Zhuang; Winson Lin; Jinyung Namkoong; Hsung Jai Im; Stanley Y. Chen
- Web page: https://patentgrep.com/patent/US10484167B2

## CPC

- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- H03K 19/017509: {Interface arrangements}
- H03L 7/0814: {the phase shifting device being digitally controlled}
- H04L 7/0025: {interpolation of clock signal}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

## Claims

### Claim 1

A circuit for receiving a signal in an integrated circuit, the circuit comprising:
a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a receiver output clock;
a clock and data recovery circuit configured to receive the sampled data and the receiver output clock and to generate a first phase interpolator code and a second phase interpolator code; and
a phase interpolator configured to receive the first phase interpolator code and the second phase interpolator code;
wherein the phase interpolator generates a first phase interpolator control signal and second phase interpolator control signal during a clock cycle based upon the first phase interpolator code and the second phase interpolator code generated for the clock cycle; and
wherein the sampler receives, from the phase interpolator, a first recovered clock signal based upon the first phase interpolator control signal and a second recovered clock signal based upon the second phase interpolator control signal.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein each of the first phase interpolator control signal and the second phase interpolator control signal comprises a phase selection signal and a weighting signal.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the first phase interpolator control signal is associated with a first half of the clock cycle and the second phase interpolator control signal is associated with a second half of the clock cycle.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the first phase interpolator control signal is determined based upon the second phase interpolator control signal.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the phase interpolator determines a change in the first phase interpolator code from a first clock cycle to a second clock cycle, and generating the first phase interpolator control signal and the second phase interpolator control signal for the clock cycle comprises applying, in the middle of the clock cycle, the second phase interpolator code that comprises the first phase interpolator code adjusted by a portion of the change in the first phase interpolator code.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the second phase interpolator code comprises the first phase interpolator code adjusted by one half of the change in the first phase interpolator code from the first clock cycle to the second clock cycle.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the second phase interpolator control signal generated during the clock cycle is based upon a comparison of bits of a current phase interpolator code and a next phase interpolator code.

### Claim 8 (depends on 7)

The circuit of claim 7, wherein the second phase interpolator control signal generated during the clock cycle is based upon the next phase interpolator code if no boundary crossing is detected.

### Claim 9 (depends on 7)

The circuit of claim 7, wherein the second phase interpolator control signal generated during the clock cycle is based upon the next phase interpolator code if a boundary crossing in a positive direction is detected.

### Claim 10 (depends on 7)

The circuit of claim 7, wherein the second phase interpolator control signal generated during the clock cycle is based upon the current phase interpolator code if a boundary crossing in a negative direction is detected.

### Claim 11

A method of receiving a signal in an integrated circuit, the method comprising:
receiving an input data signal;
generating sampled data and a receiver output clock based upon the input data signal;
generating a first phase interpolator code and a second phase interpolator code based upon the sampled data and the receiver output clock;
receiving the first phase interpolator code and the second phase interpolator code at a phase interpolator;
generating a first phase interpolator control signal and a second phase interpolator control signal during a clock cycle based upon the first phase interpolator code and the second phase interpolator code generated for the clock cycle; and
receiving, at a sampler, a first recovered clock signal based upon the first phase interpolator control signal and a second recovered clock signal based upon the second phase interpolator control signal.

### Claim 12 (depends on 11)

The method of claim 11, wherein receiving the first phase interpolator code and the second phase interpolator code at a phase interpolator comprises receiving a phase selection signal and a weighting signal.

### Claim 13 (depends on 11)

The method of claim 11, wherein generating the first phase interpolator control signal and the second phase interpolator control signal comprises generating the first phase interpolator control signal associated with a first half of the clock cycle and the second phase interpolator control signal associated with a second half of the clock cycle.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first phase interpolator control signal is determined based upon the second phase interpolator control signal.

### Claim 15 (depends on 11)

The method of claim 11, further comprising determining a change in the first phase interpolator code from a first clock cycle to a second clock cycle, wherein generating the first phase interpolator control signal and the second phase interpolator control signal during the clock cycle comprises applying, in the middle of the clock cycle, the second phase interpolator code that comprises the first phase interpolator code adjusted by a portion of the change in the first phase interpolator code.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second phase interpolator code comprises the first phase interpolator code adjusted by one half of the change in the first phase interpolator code from the first clock cycle to the second clock cycle.

### Claim 17 (depends on 11)

The method of claim 11, wherein generating the second phase interpolator control signal during the clock cycle comprises generating the second phase interpolator control signal based upon a comparison of bits of a current phase interpolator code and a next phase interpolator code.

### Claim 18 (depends on 17)

The method of claim 17, wherein generating the second phase interpolator control signal during the clock cycle comprises generating the second phase interpolator control signal based upon the next phase interpolator code if no boundary crossing is detected.

### Claim 19 (depends on 17)

The method of claim 17, wherein generating the second phase interpolator control signal during the clock cycle comprises generating the second phase interpolator control signal based upon the next phase interpolator code if a boundary crossing in a positive direction is detected.

### Claim 20 (depends on 17)

The method of claim 17, wherein generating the second phase interpolator control signal during the clock cycle comprises generating the second phase interpolator control signal based upon the current phase interpolator code in a boundary crossing if a negative direction is detected.