# US 10,484,166 B2 · Receiver

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- Number: US 10,484,166 B2
- Document ID: US10484166B2
- Status: Granted
- Kind: B2
- Application number: 15/739,452
- Filed: 2016-09-05
- Published: 2018-07-05
- Granted: 2019-11-19
- Earliest claimed: 2015-09-28
- Assignees: Denso Corporation
- Applicants: Denso Corporation
- Inventors: Nobuaki Matsudaira
- Web page: https://patentgrep.com/patent/US10484166B2

## CPC

- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- H03L 7/06: using a reference signal applied to a frequency- or phase-locked loop
- H04B 1/10: Means associated with receiver for limiting or suppressing noise or interference
- H04B 3/06: by the transmitted signal
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- H04L 7/10: Arrangements for initial synchronisation
- H04L 12/40: Bus networks
- H04L 12/40013: {Details regarding a bus controller}
- H04L 25/03: Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L 25/03012: {operating in the time domain (H04L25/03165, H04L25/03178 take precedence)}
- H04L 25/03146: {with a recursive structure (H04L25/03127 takes precedence)}
- H04L 63/12: {Applying verification of the received information (cryptographic mechanisms or cryptographic arrangements for data integrity or data verification H04L9/32)}
- H03L 2207/50: All digital phase-locked loop
- H04L 7/0062: {detection of error based on data decision error, e.g. Mueller type detection}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04B: TRANSMISSION

## Abstract

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

## Claims

### Claim 1

A receiver comprising:
an A/D converter that performs an analog digital conversion to an input signal;
an equalizer that equalizes an output of the A/D converter, eliminates an inter-code interference and obtains a data output;
a timing recovery part that generates a recovery clock by using the data output of the equalizer;
a detector that detects a timing when the input signal varies from a non-signal state and has reached a predetermined threshold; and
an initial phase setting part that sets as an initial phase of the recovery clock from the timing recovery part, a timing when a predetermined time has elapsed after the timing detected by the detector, wherein:
the timing recovery part includes a phase lock loop that outputs a reference clock and a divider that divides the reference clock of the phase lock loop; and
when the recovery clock is generated, the phase lock loop outputs the reference clock, with the initial phase of the recovery clock set by the initial phase setting part as a start, the divider starts to divide the frequency of the reference clock, generates dual-phase clocks and generates the recovery clock corresponding to the dual-phase clocks, and wherein
the detector includes a comparator arranged in parallel with the A/D converter;
the detector detects the timing that has reached the threshold by the comparator and obtains a output signal; and
the initial phase setting part includes a delay circuit that delays outputs the output signal to the timing recovery part with a delay of the output signal of the comparator for a predetermined time, and obtains the initial phase of the recovery clock.

### Claim 2 (depends on 1)

The receiver according to claim 1, wherein:
the predetermined time is set in advance so that the input signal of the A/D converter starts to vary from the no-signal state to a vicinity of a maximum value.

### Claim 3 (depends on 1)

The receiver according to claim 1, wherein:
the receiver is provided in an on-board apparatus.