# US 10,484,165 B2 · Latency buffer circuit with adaptable time shift > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,165 B2 - Document ID: US10484165B2 - Status: Granted - Kind: B2 - Application number: 15/846,560 - Filed: 2017-12-19 - Published: 2019-06-20 - Granted: 2019-11-19 - Earliest claimed: 2017-12-19 - Assignees: STMicroelectronics International N.V. - Applicants: STMicroelectronics International N.V. - Inventors: Rupesh Singh; Ankur Bal - Web page: https://patentgrep.com/patent/US10484165B2 ## CPC - H04L 7/005: {Correction by an elastic buffer} - G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation - H04J 3/047: {Distributors with transistors or integrated circuits} - H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation} - H04L 7/0012: {by comparing receiver clock with transmitter clock} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time. ## Claims ### Claim 1 A circuit, comprising: a multiplexer having a plurality of inputs configured to receive data words in parallel and having an output configured to output selected ones of the received data words in series in response to a select signal; a first-in first-out (FIFO) circuit configured to supply the data words in parallel in response to an edge of a master clock signal; and a timing control circuit configured to generate the select signal and the master clock signal in response to a temporal shift signal and a system clock signal, wherein the timing control circuit responds to an assertion of the temporal shift signal by modifying a duty cycle of the master clock signal and controlling a sequence of values for the select signal. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the temporal shift signal is a forward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to skip at least one count value in the sequence of values for the select signal. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the timing control circuit reduces the duty cycle of the master clock signal to account for the skipping of said at least one count value in the sequence of values for the select signal. ### Claim 4 (depends on 2) The circuit of claim 2, wherein modification of the duty cycle of the master clock signal comprises a reduction of a length of phase of the master clock signal to account for the skipping of said at least one count value in the sequence of values for the select signal. ### Claim 5 (depends on 2) The circuit of claim 2, wherein modification of the duty cycle of the master clock signal causes a next edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur earlier in time so as to advance multiplexer output of the selected ones of the received data words in series. ### Claim 6 (depends on 2) The circuit of claim 2, further comprising a control circuit configured to detect a backward temporal offset of a series of data words output from the multiplexer and assert the forward shift signal. ### Claim 7 (depends on 1) The circuit of claim 1, wherein the temporal shift signal is a backward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to hold at least one count value in the sequence of values for the select signal for a longer time than other count values in the sequence of values for the select signal. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the timing control circuit increases the duty cycle of the master clock signal to account for the holding of said at least one count value in the sequence of values for the select signal. ### Claim 9 (depends on 7) The circuit of claim 7, wherein modification of the duty cycle of the master clock signal comprises an increase of a length of phase of the master clock signal to account for the holding of said at least one count value in the sequence of values for the select signal. ### Claim 10 (depends on 7) The circuit of claim 7, wherein modification of the duty cycle of the master clock signal causes a next edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur later in time so as to delay multiplexer output of the selected ones of the received data words in series. ### Claim 11 (depends on 7) The circuit of claim 7, further comprising a control circuit configured to detect a forward temporal offset of a series of data words output from the multiplexer and assert the temporal shift signal. ### Claim 12 A circuit, comprising: a multiplexer having a plurality of inputs configured to receive data words in parallel and having an output configured to output selected ones of the received data words in series in response to a select signal; a first-in first-out (FIFO) circuit configured to supply the data words in parallel in response to an edge of a master clock signal; and a timing control circuit configured to generate the select signal and the master clock signal in response to a temporal shift signal and a system clock signal, wherein the timing control circuit responds to an assertion of the temporal shift signal by shifting timing of said edge of the master clock signal and controlling a sequence of values for the select signal that are generated within one cycle of the master clock signal. ### Claim 13 (depends on 12) The circuit of claim 12, wherein the temporal shift signal is a forward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to skip at least one count value in the sequence of values for the select signal that are generated within one cycle of the master clock signal. ### Claim 14 (depends on 13) The circuit of claim 13, wherein the timing control circuit causes the edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur earlier in time due to the skipping of said at least one count value in the sequence of values for the select signal. ### Claim 15 (depends on 13) The circuit of claim 13, further comprising a control circuit configured to detect a backward temporal offset of a series of data words output from the multiplexer and assert the forward shift signal. ### Claim 16 (depends on 12) The circuit of claim 12, wherein the temporal shift signal is a backward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to hold at least one count value in the sequence of values for the select signal for a longer time than other count values in the sequence of values for the select signal. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the timing control circuit causes the edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur later in time due to the holding of said at least one count value in the sequence of values for the select signal. ### Claim 18 (depends on 16) The circuit of claim 16, further comprising a control circuit configured to detect a forward temporal offset of a series of data words output from the multiplexer and assert the backward shift signal. ### Claim 19 A method, comprising: providing a plurality of data words in parallel in response to an edge of a master clock signal; serially selecting ones of the received plurality of data words in response to a sequence of values of a select signal; outputting the serially selecting ones of the received plurality of data words in a serial stream of data words; detecting a temporal offset of said serial stream of data words; controlling the sequence of values for the select signal that are generated within one cycle of the master clock signal to: skip at least one count value in the sequence of values if the detected temporal offset is a backward temporal offset; and hold at least one count value in the sequence of values for a longer period of time if the detected temporal offset is a forward temporal offset; and shifting timing of the edge of the master clock signal to account for the controlled sequence of values for the select signal. ### Claim 20 (depends on 19) The method of claim 19, wherein shifting timing causes the edge of the master clock signal causing the plurality of data words to be provided in parallel to occur earlier in time due to the skipping of said at least one count value in the sequence of values for the select signal. ### Claim 21 (depends on 19) The method of claim 19, wherein shifting timing causes the edge of the master clock signal causing the plurality of data words to be provided in parallel to occur later in time due to the holding of said at least one count value in the sequence of values for the select signal. ### Claim 22 A method, comprising: providing a plurality of data words in parallel in response to an edge of a master clock signal; serially selecting ones of the received plurality of data words in response to a sequence of values of a select signal; outputting the serially selecting ones of the received plurality of data words in a serial stream of data words; detecting a temporal offset of said serial stream of data words; controlling the sequence of values for the select signal that are generated within one cycle of the master clock signal to skip at least one count value in the sequence of values if the detected temporal offset is a backward temporal offset; and shifting timing of the edge of the master clock signal to account for the controlled sequence of values for the select signal. ### Claim 23 (depends on 22) The method of claim 22, wherein shifting timing comprises skipping of said at least one count value in the sequence of values for the select signal in order to cause the edge of the master clock signal to occur earlier in time. ### Claim 24 A method, comprising: providing a plurality of data words in parallel in response to an edge of a master clock signal; serially selecting ones of the received plurality of data words in response to a sequence of values of a select signal; outputting the serially selecting ones of the received plurality of data words in a serial stream of data words; detecting a temporal offset of said serial stream of data words; controlling the sequence of values for the select signal that are generated within one cycle of the master clock signal to hold at least one count value in the sequence of values for a longer period of time if the detected temporal offset is a forward temporal offset; and shifting timing of the edge of the master clock signal to account for the controlled sequence of values for the select signal. ### Claim 25 (depends on 24) The method of claim 24, wherein shifting timing comprises holding of said at least one count value in the sequence of values for the select signal in order to cause the edge of the master clock signal to occur later in time.