# US 10,484,164 B2 · Clock and data recovery for pulse based multi-wire link

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- Number: US 10,484,164 B2
- Document ID: US10484164B2
- Status: Granted
- Kind: B2
- Application number: 16/243,647
- Filed: 2019-01-09
- Published: 2019-05-16
- Granted: 2019-11-19
- Earliest claimed: 2015-04-13
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Shoichiro Sengoku
- Web page: https://patentgrep.com/patent/US10484164B2

## CPC

- H04L 7/0045: {Correction by a latch cascade}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- H03K 5/13: Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K 5/133: using a chain of active delay devices
- H03K 5/1534: Transition or edge detectors
- H04L 7/0037: {Delay of clock signal}
- H04L 7/0087: {Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 25/49: using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

## Claims

### Claim 1

A clock recovery circuit, comprising:
a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals;
combinational logic configured to provide a second pulse in response to the first pulse;
a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse; and
a plurality of output flip-flops configured to capture the first state when triggered by the third pulse,
wherein the first state identifies which of the plurality of input signals has received input pulses.

### Claim 2 (depends on 1)

The clock recovery circuit of claim 1, further comprising:
a one-shot circuit configured to fix a duration of the second pulse.

### Claim 3 (depends on 1)

The clock recovery circuit of claim 1, wherein the first state is output as a digit of a multi-digit number.

### Claim 4 (depends on 3)

The clock recovery circuit of claim 3, wherein the plurality of input signals is received from a multi-wire interface that comprises N wires, and wherein the multi-digit number is expressed as a base (2N−1) number.

### Claim 5 (depends on 3)

The clock recovery circuit of claim 3, wherein the plurality of input signals is received from a two-wire interface, and wherein the multi-digit number is expressed as a ternary number.

### Claim 6 (depends on 3)

The clock recovery circuit of claim 3, wherein the plurality of input signals is received from a three-wire interface, and wherein the multi-digit number is expressed as a septenary number.

### Claim 7 (depends on 1)

The clock recovery circuit of claim 1, wherein the plurality of input signals is received from a capacitively-coupled multi-wire interface.

### Claim 8 (depends on 1)

The clock recovery circuit of claim 1, wherein the plurality of input signals is received from an inductively-coupled multi-wire interface.

### Claim 9 (depends on 1)

The clock recovery circuit of claim 1, wherein the plurality of input signals is received from an optical interface.

### Claim 10 (depends on 1)

The clock recovery circuit of claim 1, further comprising:
a counter configured to count a number of transitions on one or more wires occurring between consecutive pulses provided on the receive clock.