# US 10,484,130 B2 · Method and device for parallel polar code encoding/decoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,130 B2 - Document ID: US10484130B2 - Status: Granted - Kind: B2 - Application number: 15/717,745 - Filed: 2017-09-27 - Published: 2018-04-05 - Granted: 2019-11-19 - Earliest claimed: 2016-09-30 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Huazi Zhang; Gongzheng Zhang; Rong Li; Jun Wang; Wen Tong; Yiqun Ge - Web page: https://patentgrep.com/patent/US10484130B2 ## CPC - H04L 1/0041: {Arrangements at the transmitter end} - H03M 13/13: Linear codes - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 1/0058: {Block-coded modulation} - H04L 1/0063: {Single parity check} - H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Embodiments of this disclosure enhance the error detection performance of parallel polar encoding by cross-concatenating parity bits between segments of information bits transmitted over different sets of sub-channels. In one embodiment, a first segment of information bits is transmitted over a first set of sub-channels, and at least a second segment of information bits, and a masked parity bit, are transmitted over a second set of sub-channels. A value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits. The bitwise combination may be a bitwise AND, a bitwise OR, or a bitwise XOR of the respective parity bits. ## Claims ### Claim 1 A method for polar code encoding, the method comprising: transmitting at least a first segment of information bits over a first set of sub-channels; and transmitting at least a second segment of information bits and a masked parity bit over a second set of sub-channels, wherein a value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits, the second set of sub-channels being different than the first set of sub-channels. ### Claim 2 (depends on 1) The method of claim 1, wherein the first parity bit is computed directly from the first segment of information bits, and the second parity bit is computed directly from the second segment of information bits. ### Claim 3 (depends on 1) The method of claim 1, further comprising: mapping the first segment of information bits to sub-channels in the first set of sub-channels; mapping the second segment of information bits to sub-channels in the second set of sub-channels; and computing at least the first parity bit based on the first segment of information bits in the first set of sub-channels and at least the second parity bit based on the second segment of information bits in the second set of sub-channels. ### Claim 4 (depends on 1) The method of claim 1, wherein the masked parity bit is transmitted over a single sub-channel in the second set of sub-channels. ### Claim 5 (depends on 4) The method of claim 4, wherein none of the first parity bit, the second parity bit, and the masked parity bit are transmitted over the first set of sub-channels. ### Claim 6 (depends on 4) The method of claim 4, wherein the masked parity bit is transmitted over both a single sub-channel in the second set of sub-channels and a single sub-channel in the first set of sub-channels. ### Claim 7 (depends on 4) The method of claim 4, wherein the first parity bit is transmitted over a single sub-channel in the first set of sub-channels. ### Claim 8 (depends on 4) The method of claim 4, wherein the first parity bit and the second parity bit are transmitted over different sub-channels in the second set of sub-channels. ### Claim 9 (depends on 8) The method of claim 8, wherein neither the first parity bit nor the second parity bit are transmitted over the first set of sub-channels. ### Claim 10 (depends on 8) The method of claim 8, wherein the first parity bit and the second parity bit are transmitted over the first set of sub-channels. ### Claim 11 (depends on 4) The method of claim 4, wherein the first parity bit is transmitted over a single sub-channel in the second set of sub-channels without being transmitted over any sub-channel in the first set of sub-channels, and wherein the second parity bit is transmitted over a single sub-channel in the first set of sub-channels without being transmitted over any sub-channel in the second set of sub-channels. ### Claim 12 (depends on 1) The method of claim 1, further comprising: computing the masked parity bit according to a bitwise AND of the first parity bit and at least the second parity bit. ### Claim 13 (depends on 1) The method of claim 1, further comprising: computing the masked parity bit according to a bitwise OR of the first parity bit and at least the second parity bit. ### Claim 14 (depends on 1) The method of claim 1, further comprising: computing the masked parity bit according to a bitwise XOR of the first parity bit and at least the second parity bit. ### Claim 15 (depends on 1) The method of claim 1, further comprising: before transmitting, polar encoding at least the first segment of information bits; and separately polar encoding at least the second segment of information bits and the masked parity bit. ### Claim 16 (depends on 1) The method of claim 1, wherein the masked parity bit is a cyclic redundancy check (CRC) bit, a parity check bit, or an error correcting code (ECC) bit. ### Claim 17 An apparatus comprising: a processor; and a non-transitory computer readable storage medium storing programming for execution by the processor, the programming including instructions to: transmit at least a first segment of information bits over a first set of sub-channels; and transmit at least a second segment of information bits, and a masked parity bit, over a second set of sub-channels, wherein a value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits, the second set of sub-channels being different than the first set of sub-channels. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the first parity bit is computed directly from the first segment of information bits, and the second parity bit is computed directly from the second segment of information bits. ### Claim 19 A method for polar code decoding, the method comprising: receiving a first polar-encoded bit-stream carrying at least first segment of information bits over a first set of sub-channels; and receiving a second polar-encoded bit-stream carrying at least a second segment of information bits and a masked parity bit over a second set of sub-channels, wherein a value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits, the second set of sub-channels being different than the first set of sub-channels. ### Claim 20 (depends on 19) The method of claim 19, wherein the first parity bit is computed directly from the first segment of information bits, and the second parity bit is computed directly from the second segment of information bits. ### Claim 21 (depends on 19) The method of claim 19, further comprising: performing error detection on the first segment of information bits received over the first set of sub-channels in accordance with at least the masked parity bit received over the first set of sub-channels. ### Claim 22 An apparatus comprising: a processor; and a non-transitory computer readable storage medium storing programming for execution by the processor, the programming including instructions to: receive a first polar-encoded bit-stream carrying at least first segment of information bits over a first set of sub-channels; and receive a second polar-encoded bit-stream carrying at least a second segment of information bits and a masked parity bit over a second set of sub-channels, wherein a value of the masked parity bit is equal to a bitwise combination of a first parity bit computed from the first segment of information bits and a second parity bit computed from the second segment of information bits, the second set of sub-channels being different than the first set of sub-channels. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the programming further includes instructions to perform error detection on the first segment of information bits received over the first set of sub-channels in accordance with at least the masked parity bit received over the first set of sub-channels. ### Claim 24 (depends on 22) The apparatus of claim 22, wherein the first parity bit is computed directly from the first segment of information bits, and the second parity bit is computed directly from the second segment of information bits.