# US 10,484,041 B2 · Glitch-free wide supply range transceiver for integrated circuits

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- Number: US 10,484,041 B2
- Document ID: US10484041B2
- Status: Granted
- Kind: B2
- Application number: 15/703,800
- Filed: 2017-09-13
- Published: 2019-03-14
- Granted: 2019-11-19
- Earliest claimed: 2017-09-13
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Sabarathnam Ekambaram; VSS Prasad Babu Akurathi; Milind Goel; Hari Bilash Dubey
- Web page: https://patentgrep.com/patent/US10484041B2

## CPC

- H04B 1/586: {using an electronic circuit}
- H03K 19/018521: {of complementary type, e.g. CMOS}
- H04B 1/005: {adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges}
- H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)}
- H04B 1/44: Transmit/receive switching
- H04B: TRANSMISSION
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An example receiver includes: a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal; a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver; a control circuit coupled to the pad splitter circuit and the wide-range receiver; and a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

## Claims

### Claim 1

A transmitter, comprising:
an input circuit configured to couple a logic signal to a first node and a second node;
a first level-shifter having an input coupled to the first node;
a first pre-driver having an input coupled to an output of the first level-shifter;
a second-level shifter having an input coupled to the second node, the second level-shifter is configured to perform a first level shift of the logic signal to generate a first logic signal and a second level shift of the logic signal to generate a second logic signal, and wherein an output of the second level-shifter includes the first logic signal and the second logic signal;
a second pre-driver having an input coupled to the output of the second level-shifter, the second pre-driver configured to generate an output signal having a first voltage swing in a first mode and a second voltage swing in a second mode, the second pre-driver comprising a stack of a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor coupled between a supply node and a reference node, a gate of the first p-channel transistor receiving the first logic signal, a gate of the second n-channel transistor receiving the second logic signal, and gates of the second p-channel transistor and the first n-channel transistor receiving a first and second bias voltages, respectively; and
a driver including a stack of a top p-channel transistor, a bottom p-channel transistor, a top n-channel transistor, and a bottom n-channel transistor coupled between a the supply node and a ground node, a gate of the top p-channel transistor coupled to receive the output signal of the second pre-driver, a gate of the bottom n-channel transistor coupled to an output of the first pre-driver, and gates of the bottom p-channel transistor and the top n-channel transistor coupled to receive the first and second bias voltages, respectively.

### Claim 2 (depends on 1)

The transmitter of claim 1, wherein the second pre-driver comprises:
a third p-channel transistor and a third n-channel transistor coupled between the second p-channel transistor and the first n-channel transistor, a gate of the third p-channel transistor coupled to a source of the third n-channel transistor and a drain of the first n-channel transistor, a gate of the third n-channel transistor coupled to a source of the third p-channel transistor and a drain of the second p-channel transistor.

### Claim 3 (depends on 1)

The transmitter of claim 1, wherein the second pre-driver comprises:
a slew control circuit coupled between the second n-channel transistor and the reference node.

### Claim 4 (depends on 1)

The transmitter of claim 1, wherein the second pre-driver comprises:
a transmission gate coupled between the gate of the first p-channel transistor and a gate of the second n-channel transistor, the transmission gate including a first control terminal coupled to receive a first enable signal and a second control terminal coupled to receive a second enable signal.

### Claim 5 (depends on 4)

The transmitter of claim 4, wherein the second pre-driver comprises:
fourth and fifth n-channel transistors coupled between a drain of the first p-channel transistor and a drain of the second n-channel transistor, a gate of the fourth n-channel transistor coupled to receive the second bias voltage and a gate of the fifth n-channel transistor coupled to receive the first enable signal.

### Claim 6

A receiver, comprising:
a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal;
a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver and further comprising:
first, second, and third p-channel transistors coupled between a supply node and a top input node, a gate of the first p-channel transistor coupled to receive a first enable voltage, a gate of the second p-channel transistor coupled to receive a first bias voltage, and a gate of the third p-channel transistor coupled to receive the second logic signal;
a first n-channel transistor coupled between a bottom input node and a reference node, a gate of the first n-channel transistor coupled to receive the second logic signal; and
a first transmission gate coupled between the top input node and the bottom input node;
a control circuit coupled to the pad splitter circuit and the wide-range receiver; and
a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

### Claim 7 (depends on 6)

The receiver of claim 6, wherein the wide-range receiver comprises:
fourth and fifth p-channel transistors coupled between the supply node and the top input node, a gate of the fourth p-channel transistor coupled to receive a second enable voltage, and a gate of the fifth p-channel transistor coupled to receive the first logic signal; and
sixth and seventh p-channel transistors, and second and third n-channel transistors(MNT0, MN4), coupled between the top input node and the bottom input node, a gate of the sixth p-channel transistor coupled to receive the first bias voltage, a gate of the third n-channel transistor coupled to receive a second bias voltage.

### Claim 8 (depends on 7)

The receiver of claim 7, wherein the wide-range receiver comprises:
eighth and ninth p-channel transistors coupled between the supply node and the top input node; and
tenth and eleventh p-channel transistors coupled between the supply node and a top output node;
where a gate of the eighth p-channel transistor is coupled to a gate of the tenth p-channel transistor, a gate of the ninth p-channel transistor is coupled to the top output node, and a gate of the eleventh p-channel transistor is coupled to the top input node.

### Claim 9 (depends on 8)

The receiver of claim 8, wherein the wide-range receiver comprises:
twelfth and thirteenth p-channel transistors, and fourth and fifth n-channel transistors coupled between the top output node and a bottom output node, a gate of the twelfth p-channel transistor coupled to receive the first bias voltage, a gate of the fifth n-channel transistor coupled to receive the second bias voltage.

### Claim 10 (depends on 9)

The receiver of claim 9, wherein the wide-range receiver comprises:
a sixth n-channel transistor coupled between the bottom input node and the reference node;
a seventh n-channel transistor coupled between the bottom output node and the reference node;
wherein a gate of the sixth n-channel transistor is coupled to the bottom output node and a gate of the seventh n-channel transistor(MN8) is coupled to the bottom input node.

### Claim 11 (depends on 10)

The receiver of claim 10, wherein the wide-range receiver comprises:
a second transmission gate coupled between the top output node and the bottom output node.

### Claim 12 (depends on 6)

The receiver of claim 6, wherein the wide-range receiver includes first circuitry that provides a first resistance and second circuitry that provides a second resistance, the first resistance in parallel to the second resistance, and third circuitry that provides a third resistance, coupled in series with the parallel combination of the first resistance, and wherein the combination of the first, second, and third resistance controls a trigger point of the wide-range receiver.

### Claim 13

A transceiver, comprising:
a transmitter that includes:
an input circuit configured to couple a logic signal to a first node and a second node;
a first level-shifter having an input coupled to the first node;
a first pre-driver having an input coupled to an output of the first level-shifter;
a second-level shifter having an input coupled to the second node;
a second pre-driver having an input coupled to an output of the second level-shifter, the second pre-driver configured to generate an output signal having a first voltage swing in a first mode and a second voltage swing in a second mode; and
a driver including a stack of a top p-channel transistor, a bottom p-channel transistor, a top n-channel transistor, and a bottom n-channel transistor coupled between a supply node and a ground node, a gate of the top p-channel transistor coupled to receive the output signal of the second pre-driver, a gate of the bottom n-channel transistor coupled to an output of the first pre-driver, and gates of the bottom p-channel transistor and the top n-channel transistor coupled to receive first and second bias voltages, respectively; and
a receiver that includes:
a pad splitter circuit coupled to a pad, the pad splitter circuit configured to generate a first logic signal and a second logic signal;
a wide-range receiver coupled to the pad splitter circuit to receive the first and second logic signals, the wide-range receiver comprising a combination of a first Schmitt trigger receiver and a second Schmitt trigger receiver and further comprising first circuitry that provides a first resistance and second circuitry that provides a second resistance, the first resistance in parallel to the second resistance, and third circuitry that provides a third resistance, coupled in series with the parallel combination of the first resistance, and wherein the combination of the first, second, and third resistance controls a trigger point of the wide-range receiver;
a control circuit coupled to the pad splitter circuit and the wide-range receiver; and
a bias generator circuit coupled to the pad splitter circuit and the wide-range receiver.

### Claim 14 (depends on 13)

The transceiver of claim 13, wherein the second level-shifter is configured to perform a first level shift of the logic signal to generate a first logic signal and a second level shift of the logic signal to generate a second logic signal, and wherein the output of the second level-shifter includes the first logic signal and the second logic signal.

### Claim 15 (depends on 14)

The transceiver of claim 14, wherein the second pre-driver comprises:
a stack of a first p-channel transistor, a second p-channel transistor, a first n-channel transistor, and a second n-channel transistor coupled between the supply node and a reference node, a gate of the first p-channel transistor receiving the first logic signal, a gate of the second n-channel transistor receiving the second logic signal, and gates of the second p-channel transistor and the first n-channel transistor receiving the first and second bias voltages, respectively.

### Claim 16 (depends on 15)

The transceiver of claim 15, wherein the second pre-driver comprises:
a third p-channel transistor and a third n-channel transistor coupled between the second p-channel transistor and the first n-channel transistor, a gate of the third p-channel transistor coupled to a source of the third n-channel transistor and a drain of the first n-channel transistor, a gate of the third n-channel transistor coupled to a source of the third p-channel transistor and a drain of the second p-channel transistor.