# US 10,484,025 B2 · Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power amplifiers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,025 B2 - Document ID: US10484025B2 - Status: Granted - Kind: B2 - Application number: 15/661,749 - Filed: 2017-07-27 - Published: 2017-11-09 - Granted: 2019-11-19 - Earliest claimed: 2013-04-24 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Lisette L. Zhang; Oleksandr Gorbachov - Web page: https://patentgrep.com/patent/US10484025B2 ## CPC - H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)} - H03F 3/195: in integrated circuits - H03F 3/213: in integrated circuits - H03F 3/24: of transmitter output stages - H04B 1/16: Circuits - H04B 1/40: Circuits - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/465: Power sensing - H04B 1/0067: {with one or more circuit blocks in common for different bands} - H04B 2001/0408: {with power amplifiers} - H10W 44/226: {for HF amplifiers} - H10W 44/234: {Arrangements for impedance matching} - H10W 44/241: {for passive devices or passive elements} - H10W 44/248: {for antennas} - H10W 44/255: {for operation at multiple different frequencies} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H04B: TRANSMISSION - H03F: AMPLIFIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. ## Claims ### Claim 1 An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns, the integrated circuit architecture comprising: a first operating frequency region corresponding to a physical area on the die structure including a first transmit chain, a first receive chain, and a first antenna conductive pad, the first operating frequency region being defined by a first outer periphery and an opposed first inner periphery; a second operating frequency region corresponding to a physical area on the die structure including a second transmit chain, a second receive chain, and a second antenna conductive pad, the second operating frequency region being defined by a second outer periphery and an opposed second inner periphery; and a shared region of the die structure corresponding to a physical area thereon and defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the first inner periphery of the first operating frequency region and the second inner periphery of the second operating frequency region both being adjacent to the shared region, the shared region including either one or both of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. ### Claim 2 (depends on 1) The integrated circuit architecture of claim 1 wherein the first operating frequency region of the die structure includes a first switch disposed thereon selectively connecting the first antenna conductive pad to the first transmit chain and the first receive chain, and the second operating frequency region of the die structure includes a second switch disposed thereon selectively connecting the second antenna conductive pad to the second transmit chain and the second receive chain. ### Claim 3 (depends on 1) The integrated circuit architecture of claim 1 wherein the first transmit chain includes at least one first operating frequency power amplifier. ### Claim 4 (depends on 1) The integrated circuit architecture of claim 1 wherein the first receive chain includes at least one first operating frequency low noise amplifier. ### Claim 5 (depends on 1) The integrated circuit architecture of claim 1 wherein the second transmit chain includes at least one second operating frequency power amplifier. ### Claim 6 (depends on 1) The integrated circuit architecture of claim 1 wherein the second receive chain includes at least one second operating frequency low noise amplifier. ### Claim 7 An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns, the integrated circuit architecture comprising: a first operating frequency region corresponding to a physical area on the die structure including a first transmit chain, a first receive chain, and a first antenna conductive pad; a second operating frequency region corresponding to a physical area on the die structure including a second transmit chain, a second receive chain, and a second antenna conductive pad; and a shared region of the die structure corresponding to a physical area thereon and defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the shared region including either one or both of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. ### Claim 8 (depends on 7) The integrated circuit architecture of claim 7 wherein the first operating frequency region of the die structure includes a first switch disposed thereon selectively connecting the first antenna conductive pad to the first transmit chain and the first receive chain, and the second operating frequency region of the die structure includes a second switch disposed thereon selectively connecting the second antenna conductive pad to the second transmit chain and the second receive chain. ### Claim 9 (depends on 7) The integrated circuit architecture of claim 7 wherein the first transmit chain includes at least one first operating frequency power amplifier. ### Claim 10 (depends on 7) The integrated circuit architecture of claim 7 wherein the first receive chain includes at least one first operating frequency low noise amplifier. ### Claim 11 (depends on 7) The integrated circuit architecture of claim 7 wherein the second transmit chain includes at least one second operating frequency power amplifier. ### Claim 12 (depends on 7) The integrated circuit architecture of claim 7 wherein the second receive chain includes at least one second operating frequency low noise amplifier. ### Claim 13 An integrated circuit architecture defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns, the integrated circuit architecture comprising: a first operating frequency region corresponding to a physical area on the die structure including a first transmit chain and a first receive chain, the first operating frequency region being defined by a first outer periphery and an opposed first inner periphery; a second operating frequency region corresponding to a physical area on the die structure including a second transmit chain and a second receive chain, the second operating frequency region being defined by a second outer periphery and an opposed second inner periphery; and a shared region of the die structure corresponding to a physical area thereon and defined by an overlapping segment of the first operating frequency region and the second operating frequency region, the first inner periphery of the first operating frequency region and the second inner periphery of the second operating frequency region both being adjacent to the shared region, the shared region including either one or both of a shared power input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. ### Claim 14 (depends on 13) The integrated circuit architecture of claim 13 wherein the first transmit chain includes at least one first operating frequency power amplifier. ### Claim 15 (depends on 14) The integrated circuit architecture of claim 14 wherein the first receive chain includes at least one first operating frequency low noise amplifier. ### Claim 16 (depends on 15) The integrated circuit architecture of claim 15 wherein the at least one first operating frequency power amplifier is disposed on the first outer periphery and the at least one first operating frequency low noise amplifier is disposed in the first inner periphery away from the at least one first operating frequency power amplifier. ### Claim 17 (depends on 14) The integrated circuit architecture of claim 14 wherein the second transmit chain includes at least one second operating frequency power amplifier. ### Claim 18 (depends on 17) The integrated circuit architecture of claim 17, further comprising: one or more ground conductive pads of the at least one first operating frequency power amplifier disposed along the first outer periphery of the first operating frequency region; and one or more ground conductive pads of the at least one second operating frequency power amplifier disposed along the second outer periphery of the second operating frequency region. ### Claim 19 (depends on 18) The integrated circuit architecture of claim 18 wherein source terminals of transistors of the at least one first operating frequency power amplifier are positioned in proximity to the one or more ground conductive pads. ### Claim 20 (depends on 13) The integrated circuit architecture of claim 13 wherein the first receive chain includes at least one first operating frequency low noise amplifier. ### Claim 21 (depends on 20) The integrated circuit architecture of claim 20 wherein the second receive chain includes at least one second operating frequency low noise amplifier. ### Claim 22 (depends on 21) The integrated circuit architecture of claim 21, further comprising: one or more ground conductive pads of the at least one first operating frequency low noise amplifier are disposed along the first inner periphery of the first operating frequency region; and one or more ground conductive pads of the at least one second operating frequency low noise amplifier are disposed along the second inner periphery of the second operating frequency region. ### Claim 23 (depends on 13) The integrated circuit architecture of claim 13 wherein the second transmit chain includes at least one second operating frequency power amplifier. ### Claim 24 (depends on 13) The integrated circuit architecture of claim 13 wherein the second receive chain includes at least one second operating frequency low noise amplifier.