# US 10,484,021 B1 · Log-likelihood ratio processing for linear block code decoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,021 B1 - Document ID: US10484021B1 - Status: Granted - Kind: B1 - Application number: 15/916,090 - Filed: 2018-03-08 - Granted: 2019-11-19 - Earliest claimed: 2018-03-08 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Gordon I. Old; Richard L. Walke - Web page: https://patentgrep.com/patent/US10484021B1 ## CPC - H03M 13/13: Linear codes - H03M 13/45: Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence) - H03M 13/615: {Use of computational or mathematical techniques} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Apparatuses and methods relating generally to a decoder. In an apparatus, a control circuit receives first-third sign signals, a partial sum signal, a function select signal, and a carry signal as an input vector to provide an output sign and a vector select. A select generation circuit receives the first and second sign signals and the partial sum signal to provide an add/subtract select signal. A subtractor subtracts from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal. Responsive to the add/subtract select signal, an adder/subtractor either adds or subtracts the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal. A multiplexer selects from the first and second absolute value signals, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select. ## Claims ### Claim 1 A decoder, comprising: a control circuit configured to receive a first sign signal, a second sign signal, a partial sum signal, a function select signal, a third sign signal, and a carry signal as an input vector to provide an output sign signal and a vector select signal; a select generation circuit configured to receive the first sign signal, the second sign signal, and the partial sum signal to provide an add/subtract select signal; a subtractor configured to subtract from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal; responsive to the add/subtract select signal, an adder/subtractor configured to either add or subtract the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal; and a multiplexer configured to select from the first absolute value signal, the second absolute value signal, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select signal. ### Claim 2 (depends on 1) The decoder according to claim 1, wherein the control circuit comprises a lookup table circuit or a combinatorial logic circuit having stored therein output vectors to select therefrom the output sign signal and the vector select signal in response to the input vector. ### Claim 3 (depends on 2) The decoder according to claim 2, further comprising: the control circuit configured to provide a preset signal responsive to a portion of the input vector and the carry signal; and an output register configured to receive the preset signal and the selected value signal to provide an output absolute value signal. ### Claim 4 (depends on 3) The decoder according to claim 3, wherein: the first sign signal and the first absolute value signal are respectively for a first sign and a first magnitude of a first log-likelihood ratio (“LLR”); the second sign signal and the second absolute value signal are respectively for a second sign and a second magnitude of a second LLR; the function select signal is to select between an F function and a G function for Successive Cancellation polar code decoding; and the control circuit is configured to provide the vector select signal for either the F function or the G function. ### Claim 5 (depends on 4) The decoder according to claim 4, wherein the difference signal is a first difference signal, and wherein the adder/subtractor responsive to the add/subtract select signal is configured to either: add the first magnitude to the second magnitude to obtain a sum value for the sum/difference signal and a carry value for the carry signal; or subtract the first magnitude from the second magnitude to obtain a second difference signal for the sum/difference signal. ### Claim 6 (depends on 5) The decoder according to claim 5, wherein the output sign signal and the output absolute value signal are a decoded output of a polar code encoded input transmitted over a channel represent by the first LLR and the second LLR. ### Claim 7 (depends on 5) The decoder according to claim 5, wherein: the multiplexer is a 4-to-1 multiplexer of a programmable logic device; and the input vector is a 6-bit input vector. ### Claim 8 (depends on 5) The decoder according to claim 5, wherein the control circuit includes a selection circuit configured to receive the carry signal, the first sign signal, the second sign signal, the partial sum signal, and the function select signal to provide the preset signal. ### Claim 9 (depends on 5) The decoder according to claim 5, wherein the lookup table circuit is configured to cross-point as between a subset of the output vectors representing subtractions with reversed orders with respect to one another. ### Claim 10 A method for decoding, comprising: receiving by a decoder a first sign signal, a second sign signal, a partial sum signal, a function select signal, a third sign signal, and a carry signal as an input vector to a control circuit thereof and a first absolute value signal and a second absolute value signal; looking up in a lookup table circuit of the control circuit an output sign signal and a vector select signal in response to the input vector; generating by a select generation circuit an add/subtract select signal in response to the first sign signal, the second sign signal, and the partial sum signal; subtracting from the first absolute value signal the second absolute value signal by a subtractor to provide the third sign signal and a difference signal; responsive to the add/subtract select signal, selectively either adding to or subtracting from the first absolute value signal the second absolute value signal by an adder/subtractor to provide the carry signal and a sum/difference signal; and selecting with a multiplexer from the first absolute value signal, the second absolute value signal, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select signal. ### Claim 11 (depends on 10) The method for decoding according to claim 10, further comprising: generating a preset signal responsive to a portion of the input vector and the carry signal; presetting an output register with the preset signal; and registering with the output register preset the selected value signal to provide an output absolute value signal. ### Claim 12 (depends on 10) The method according to claim 10, wherein: the first sign signal and the first absolute value signal are respectively for a first sign and a first magnitude of a first log-likelihood ratio (“LLR”); the second sign signal and the second absolute value signal are respectively for a second sign and a second magnitude of a second LLR; and the looking up comprises: responsive to the function select signal, selecting between an F function and a G function for Successive Cancellation polar code decoding; and providing from the control circuit the vector select signal for either the F function or the G function. ### Claim 13 (depends on 12) The method according to claim 12, wherein: the adder/subtractor responsive to the add/subtract select signal is configured to either add the first magnitude to the second magnitude or subtract the first magnitude from the second magnitude; the difference signal is a first difference signal; the adder/subtractor is configured responsive to the add/subtract select signal for either: adding the second magnitude to the first magnitude to obtain a sum value for the sum/difference signal and a carry value for the carry signal; or subtracting the first magnitude from the second magnitude to obtain a second difference signal for the sum/difference signal.