# US 10,484,014 B2 · Controller, semiconductor memory system and operating method thereof

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- Number: US 10,484,014 B2
- Document ID: US10484014B2
- Status: Granted
- Kind: B2
- Application number: 15/602,255
- Filed: 2017-05-23
- Published: 2018-01-25
- Granted: 2019-11-19
- Earliest claimed: 2016-07-21
- Assignees: SK hynix Inc.; Korea Advanced Institute of Science and Technology
- Applicants: SK hynix Inc.; Korea Advanced Institute of Science and Technology
- Inventors: Jeong-Seok Ha; Dae-Sung Kim; Su-Hwang Jeong
- Web page: https://patentgrep.com/patent/US10484014B2

## CPC

- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- G06F 11/1072: {in multilevel memories}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/611: {Specific encoding aspects, e.g. encoding by means of decoding}
- H03M 13/616: {Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations}
- G11C 2029/0411: {Online error correction}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An operating method of a controller includes generating a square message matrix of k×k; and generating an encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code, wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix, wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and wherein “α”, “β” and N have relationships represented by equations 1 and 2: α = ⌊ M N ⌋ [ Equation ⁢ ⁢ 1 ] β = M ⁢ ⁢ mod ⁢ ⁢ N [ Equation ⁢ ⁢ 2 ] where “M” represents a size of a message input from a host and “N” represents a number of message blocks forming the upper triangular matrix.

## Claims

### Claim 1

An operating method of a memory system including a controller and a memory device, the operating method comprising:
receiving a message from a host by the controller;
generating a square message matrix of k×k based on the message by the controller;
minimizing a length of each codes included in the square message matrix;
generating an encoded message by the controller which encodes the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code; and
storing the encoded message in the memory device; and
obtaining the encoded message in the memory device by the controller for decoding,
wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and
wherein “α”, “β” and N have relationships represented by equations
α
=
⌊
M
N
⌋
β
=
M
⁢
⁢
mod
⁢
⁢
N
where “M” represents a size of the message input from the host and “N” represents a number of message blocks forming the upper triangular matrix,
wherein the generating of the encoded message includes generating a parity block for each row of the square message matrix, and
wherein each size of the zero-padding blocks is the same as the parity block.

### Claim 2 (depends on 1)

The operating method of claim 1,
wherein the generating of the encoded message includes selecting the “β” numbers of message blocks from message blocks included in an (i)th diagonal matrix group according to a sequential priority of the message blocks included in the (i)th diagonal matrix group,
wherein the (i)th diagonal matrix group includes a (i+1)th diagonal matrix and a (k+1−i)th diagonal matrix, and
wherein the “i” and “k” have a relationship represented by following equation-31
1
≤
i
≤
⌊
k
2
⌋
where “i” and “k” are integers.

### Claim 3 (depends on 2)

The operating method of claim 2,
wherein the message blocks included in the (i)th diagonal matrix group have the sequence such that a message block included in the (i+1)th diagonal matrix has a sequentially higher priority than a message block included in the (k+1−i)th diagonal matrix, and such that a message block of higher row has a sequentially higher priority in a diagonal matrix, and
wherein the generating of the encoded message includes, when the “β” numbers of message blocks are selected from the (i)th diagonal matrix group, selecting (2*(n−1)*i+1)th to ((2n−1)*i)th message blocks prior to ((2n−1)*i+1)th to (2n*i)th message blocks among message blocks included in the (i)th diagonal matrix group, where “n” is an integer greater than one (1).

### Claim 4 (depends on 3)

The operating method of claim 3,
wherein the generating of the encoded message includes selecting “γ” numbers of message blocks among the “β” numbers of message blocks from a (k/2)th diagonal matrix group when the “k” is even and the “β” satisfies following equation,
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
and
wherein the “γ”, “β” and “k” have a relationship represented by following equation
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
γ
=
β
⁢
⁢
mod
⁢
⁢
k
.

### Claim 5

A memory system comprising:
a controller suitable for receiving a message from a host; and
a memory device suitable for storing an encoded message;
wherein the controller includes:
an error correction code (ECC) circuit suitable for generating a square message matrix of k×k by using the message, minimizing a length of each codes included in the square message matrix, and generating the encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code; and
a processor suitable for providing the encoded message to the memory device and obtaining the encoded message in the memory device for decoding,
wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and
wherein the “α”, “β” and “N” have relationships represented by following equations
α
=
⌊
M
N
⌋
β
=
M
⁢
⁢
mod
⁢
⁢
N
where the “M” represents a size of the message input from the host and the “N” represents a number of message blocks forming the upper triangular matrix,
wherein the error correction code (ECC) circuit further generates a parity block for each row of the square message matrix, and
wherein each size of the zero-padding blocks has the same as the parity block.

### Claim 6 (depends on 5)

The memory system of claim 5,
wherein the error correction code (ECC) circuit selects the “β” numbers of message blocks from message blocks included in an (i)th diagonal matrix group according to a sequential priority of the message blocks included in the (i)th diagonal matrix group,
wherein the (i)th diagonal matrix group includes a (i+1)th diagonal matrix and a (k+1−i)th diagonal matrix, and
wherein the “i” and “k” have a relationship represented by following equation
1
≤
i
≤
⌊
k
2
⌋
where “i” and “k” are integers.

### Claim 7 (depends on 6)

The memory system of claim 6,
wherein the message blocks included in the (i)th diagonal matrix group have the sequence such that a message block included in the (i+1)th diagonal matrix has a sequentially higher priority than a message block included in the (k+1−i)th diagonal matrix, and such that a message block of higher row has a sequentially higher priority in a diagonal matrix, and
wherein the error correction code (ECC) circuit selects, when the “β” numbers of message blocks are selected from the (i)th diagonal matrix group, (2*(n−1)*i+1)th to ((2n−1)*i)th message blocks prior to ((2n−1)*i+1)th to (2n*i)th message blocks among message blocks included in the (i)th diagonal matrix group, where “n” is an integer greater than one (1).

### Claim 8 (depends on 7)

The memory system of claim 7,
wherein the error correction code (ECC) circuit selects “γ” numbers of message blocks among the “β” numbers of message blocks from a (k/2)th diagonal matrix group when the “k” is even and the “β” satisfies following equation,
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
and
wherein the “γ”, “β” and “k” have a relationship represented by following equation
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
γ
=
β
⁢
⁢
mod
⁢
⁢
k
.

### Claim 9

An operating method of a memory system including a controller and a memory device, the operating method comprising:
reading from the memory device, by the controller, an encoded message including a square message matrix of k×k;
generating, by the controller, a decoded message by decoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code; and
providing, by the controller, the decoded message to a host,
wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and
wherein “α”, “β” and N have relationships represented by following equations
α
=
⌊
M
N
⌋
β
=
M
⁢
⁢
mod
⁢
⁢
N
where “M” represents a size of the encoded message and “N” represents a number of message blocks forming the upper triangular matrix, and
wherein a length of each codes included in the squared message matrix is minimized and each size of the zero-padding blocks is the same as a parity block for each row of the square message matrix.

### Claim 10 (depends on 9)

The operating method of claim 9,
wherein the generating of the decoded message includes selecting the “β” numbers of message blocks from message blocks included in an (i)th diagonal matrix group according to a sequential priority of the message blocks included in the (i)th diagonal matrix group,
wherein the (i)th diagonal matrix group includes a (i+1)th diagonal matrix and a (k+1−i)th diagonal matrix, and
wherein the “i” and “k” have a relationship represented by following equation
1
≤
i
≤
⌊
k
2
⌋
where “i” and “k” are integers.

### Claim 11 (depends on 10)

The operating method of claim 10,
wherein the message blocks included in the (i)th diagonal matrix group have the sequence such that a message block included in the (i+1)th diagonal matrix has a sequentially higher priority than a message block included in the (k+1−i)th diagonal matrix, and such that a message block of higher row has a sequentially higher priority in a diagonal matrix, and
wherein the generating of the encoded message includes, when the “β” numbers of message blocks are selected from the (i)th diagonal matrix group, selecting (2*(n−1)*i+1)th to ((2n−1)*i)th message blocks prior to ((2n−1)*i+1)th to (2n*i)th message blocks among message blocks included in the (i)th diagonal matrix group, where “n” is an integer greater than one (1).

### Claim 12 (depends on 11)

The operating method of claim 11,
wherein the generating of the decoded message includes selecting “γ” numbers of message blocks among the “β” numbers of message blocks from a (k/2)th diagonal matrix group when the “k” is even and the “β” satisfies following equation,
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
and
wherein the “γ”, “β” and “k” have a relationship represented by following equation
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
γ
=
β
⁢
⁢
mod
⁢
⁢
k
.

### Claim 13

A memory system comprising:
a memory device suitable for storing an encoded message; and
a controller suitable for reading the encoded message, decoding the encoded message and providing a decoded message to a host;
wherein the controller includes:
an error correction code (ECC) circuit suitable for reading from the memory device the encoded message including a square message matrix of k×k, and generating the decoded message by decoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code; and
a processor suitable for providing the decoded message to the host,
wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and
wherein the “α”, “β” and “N” have relationships represented by following equations
α
=
⌊
M
N
⌋
β
=
M
⁢
⁢
mod
⁢
⁢
N
where the “M” represents a size of the encoded message and the “N” represents a number of message blocks forming the upper triangular matrix, and
wherein a length of each codes included in the squared message matrix is minimized and each size of the zero-padding blocks is the same as a parity block for each row of the square message matrix.

### Claim 14 (depends on 13)

The memory system of claim 13,
wherein the error correction code (ECC) circuit selects the “β” numbers of message blocks from message blocks included in an (i)th diagonal matrix group according to a sequential priority of the message blocks included in the (i)th diagonal matrix group,
wherein the (i)th diagonal matrix group includes a (i+1)th diagonal matrix and a (k+1−i)th diagonal matrix, and
wherein the “i” and “k” have a relationship represented by following equation
1
≤
i
≤
⌊
k
2
⌋
where “i” and “k” are integers.

### Claim 15 (depends on 14)

The memory system of claim 14,
wherein the message blocks included in the (i)th diagonal matrix group have the sequence such that a message block included in the (i+1)th diagonal matrix has a sequentially higher priority than a message block included in the (k+1−i)th diagonal matrix, and such that a message block of higher row has a sequentially higher priority in a diagonal matrix, and
wherein the error correction code (ECC) circuit selects, when the “β” numbers of message blocks are selected from the (i)th diagonal matrix group, (2*(n−1)*i+1)th to ((2n−1)*i)th message blocks prior to ((2n−1)*i+1)th to (2n*i)th message blocks among message blocks included in the (i)th diagonal matrix group, where “n” is an integer greater than one (1).

### Claim 16 (depends on 15)

The memory system of claim 15,
wherein the error correction code (ECC) circuit selects “γ” numbers of message blocks among the “β” numbers of message blocks from a (k/2)th diagonal matrix group when the “k” is even and the “β” satisfies following equation 4,
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
and
wherein the “γ”, “β” and “k” have a relationship represented by following equation
β
⁢
⁢
mod
⁢
⁢
k
≤
k
2
γ
=
β
⁢
⁢
mod
⁢
⁢
k
.