# US 10,484,008 B2 · Memory system with on-the-fly error detection and termination and operating method thereof

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- Number: US 10,484,008 B2
- Document ID: US10484008B2
- Status: Granted
- Kind: B2
- Application number: 15/719,156
- Filed: 2017-09-28
- Published: 2019-03-28
- Granted: 2019-11-19
- Earliest claimed: 2017-09-28
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Fan Zhang; Chenrong Xiong; Abhiram Prabhakar; Aman Bhatia; Yu Cai; Naveen Kumar
- Web page: https://patentgrep.com/patent/US10484008B2

## CPC

- H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- H03M 13/1128: {Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.

## Claims

### Claim 1

A decoding method, comprising:
calculating cyclic redundancy check (CRC) parity bits for data on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data; and
terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.

### Claim 2 (depends on 1)

The method of claim 1, further comprising determining LDPC checksum in accordance with the LDPC decoding.

### Claim 3 (depends on 2)

The method of claim 2, wherein the terminating of the LDPC decoding comprises terminating the LDPC decoding when the generated CRC parity bits match with the CRC bits in the data and it is determined that the LDPC checksum is less than a predetermined threshold.

### Claim 4 (depends on 3)

The method of claim 3, wherein the terminating of the LDPC decoding further comprises outputting hard decision values in accordance with the LDPC decoding.

### Claim 5 (depends on 1)

The method of claim 1, wherein the updating of the calculated CRC parity bits comprises updating the calculated CRC parity bits by feeding predetermined bits into a CRC encoder.

### Claim 6 (depends on 1)

The method of claim 1, wherein the performing of the LDPC decoding for the data comprises processing, for each iteration of the LDPC decoding, updating messages for a circulant.

### Claim 7

A memory system, comprising:
a storage; and
a decoder coupled to the storage and suitable for:
calculating cyclic redundancy check (CRC) parity bits for data from the storage on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data; and
terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein the decoder is further suitable for determining LDPC checksum in accordance with the LDPC decoding.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein the decoder is further suitable for terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match with the CRC bits and it is determined that the LDPC checksum is less than a predetermined threshold.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the decoder is further suitable for outputting hard decision values in accordance with the LDPC decoding.

### Claim 11 (depends on 7)

The memory system of claim 7, wherein the decoder is further suitable for updating the calculated CRC parity bits by feeding predetermined bits into a CRC encoder.

### Claim 12 (depends on 7)

The memory system of claim 7, wherein the decoder is further suitable for performing of the LDPC decoding for the data by processing, for each iteration of the LDPC decoding, updating messages for a circulant.

### Claim 13

A memory controller, comprising:
a receiver suitable for receiving data; and
a decoder coupled with the receiver and suitable for:
calculating cyclic redundancy check (CRC) parity bits for data on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data; and
terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.

### Claim 14 (depends on 13)

The memory controller of claim 13, wherein the decoder is further suitable for determining LDPC checksum in accordance with the LDPC decoding.

### Claim 15 (depends on 14)

The memory controller of claim 14, wherein the decoder is further suitable for terminating the LDPC decoding, when the comparing indicates that the generated CRC parity bits match with the CRC bits and it is determined that the LDPC checksum is less than a predetermined threshold.

### Claim 16 (depends on 15)

The memory controller of claim 15, wherein the decoder is further suitable for outputting hard decision values in accordance with the LDPC decoding.

### Claim 17 (depends on 13)

The memory controller of claim 13, wherein the decoder is further suitable for updating the calculated CRC parity bits by feeding predetermined bits into a CRC encoder.

### Claim 18 (depends on 13)

The memory controller of claim 13, wherein the decoder is further suitable for performing of the LDPC decoding for the data by processing, for each iteration of the LDPC decoding, updating messages for a circulant.