# US 10,484,007 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,484,007 B2 - Document ID: US10484007B2 - Status: Granted - Kind: B2 - Application number: 15/628,857 - Filed: 2017-06-21 - Published: 2018-07-26 - Granted: 2019-11-19 - Earliest claimed: 2017-01-26 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Woo Hyun Paik - Web page: https://patentgrep.com/patent/US10484007B2 ## CPC - H03M 13/11: using multiple parity bits - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 17/16: using electrically-fusible links - G11C 29/027: {in fuses} - G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells - G11C 29/787: {using a fuse hierarchy} - H04J 3/1611: {Synchronous digital hierarchy [SDH] or SONET (H04J3/1664 takes precedence for interactions with OTN)} - H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)} - H04L 1/245: {by using the properties of transmission codes} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G11C: STATIC STORES (semiconductor memory devices H10B) - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Disclosed may be a repair information storage circuit. The repair information storage circuit may include a fuse set. A plurality of fuses included in the fuse set may be allocated to the respective bits of preliminary repair information and defect check information. The fuse allocated to the defect check information may be ruptured to store information on whether the fuse set has a defect. ## Claims ### Claim 1 A semiconductor apparatus comprising: a repair information storage circuit comprising a fuse set for storing a preliminary repair information and a defect check information; an error calculation circuit configured to generate repair information according to the preliminary repair information, and generate a validity determination bit as one piece of information in the repair information, using the preliminary repair information and the defect check information, the validity determination bit defining whether the fuse set has a defect; and a repair processing unit configured to set a fuse set latch in a memory array block in an unavailable state according to the validity determination bit, wherein the memory array block is set to the corresponding fuse set in the unavailable state. ### Claim 2 (depends on 1) The semiconductor apparatus of claim 1, wherein the memory array block is configured to decide whether to perform a repair operation based on the repair information, according to the validity determination bit. ### Claim 3 (depends on 1) The semiconductor apparatus of claim 1, wherein a fuse allocated to any one of bits contained in the preliminary repair information is an enable fuse for storing a signal indicating that a defective address is stored in the fuse set. ### Claim 4 (depends on 1) The semiconductor apparatus of claim 1, wherein the defect check information is stored in a spare fuse among a plurality of fuses included in the fuse set. ### Claim 5 (depends on 1) The semiconductor apparatus of claim 1, wherein the error calculation circuit comprises: a validity determination bit generation circuit configured to generate the validity determination bit by performing an XOR operation on the preliminary repair information and the defect check information; and a plurality of buffers configured to buffer the respective bits of the preliminary repair information excluding the validity determination bit, and output the buffered information as the repair information. ### Claim 6 (depends on 1) The semiconductor apparatus of claim 1, wherein the memory array block comprises: a plurality of memory banks each having a fuse set latch array arranged therein; and a repair processing unit configured to set the fuse set in an unavailable state according to the validity determination bit of the repair information. ### Claim 7 (depends on 6) The semiconductor apparatus of claim 6, wherein a repair operation based on the repair information is not performed corresponding to the fuse set in the unavailable state. ### Claim 8 (depends on 6) The semiconductor apparatus of claim 6, wherein a fuse set array is configured to store the repair information, read from the fuse set according to a read command, during a boot-up mode operation. ### Claim 9 (depends on 8) The semiconductor apparatus of claim 8, wherein the fuse set array is configured to store the repair information, read from the fuse set according to the read command, during the boot-up mode operation and before a normal operation. ### Claim 10 (depends on 1) The semiconductor apparatus of claim 1, wherein a repair operation corresponding to the validity determination bit is not performed when the fuse set is set in the unavailable state.