# US 10,484,005 B1 · Method and apparatus of an acoustic energy detection circuit for a pulse density modulation microphone

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- Number: US 10,484,005 B1
- Document ID: US10484005B1
- Status: Granted
- Kind: B1
- Application number: 16/380,968
- Filed: 2019-04-10
- Granted: 2019-11-19
- Earliest claimed: 2019-04-10
- Assignees: Nuvoton Technology Corporation
- Applicants: Nuvoton Technology Corporation
- Inventors: Peter Holzmann
- Web page: https://patentgrep.com/patent/US10484005B1

## CPC

- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03M 7/3042: {the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only}
- G10L 21/0232: Processing in the frequency domain
- H03G 3/301: {the gain being continuously variable}
- H03M 1/82: with intermediate conversion to time interval
- H04R 19/04: Microphones (H04R19/01 takes precedence)
- H03F 3/68: Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)}
- H03F 2200/345: Pulse density modulation being used in an amplifying circuit
- H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence)
- H04R 1/02: Casings; Cabinets {; Supports therefor;} Mountings therein (H04R1/28 takes precedence {; attachments for microphones H04R1/08; mounting of transducers in earpieces H04R1/1075})
- H04R 3/00: Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F)
- H04R 3/12: for distributing signals to two or more loudspeakers {(specially adapted for hearing aids H04R25/407)}
- H04R 19/016: {for microphones}
- H03F: AMPLIFIERS
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G10L: SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
- H03G: CONTROL OF AMPLIFICATION
- H04R: LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS (producing sounds with frequency not determined by supply frequency G10K)

## Abstract

A PDM (pulse density modulation) signal energy detection circuit includes a digital-to-analog converter circuit for receiving a PDM digital input signal and producing an analog output signal based on the PDM digital input signal. The PDM signal energy detection circuit also includes a comparator circuit for receiving the analog output signal from the digital-to-analog converter circuit and producing a pulsed signal when a magnitude of the analog output signal exceeds a pre-set threshold. The PDM signal energy detection circuit also has a counter circuit for receiving the pulsed signal from the comparator circuit and producing an energy detection signal when a number of consecutive pulsed signals exceed a pre-set count.

## Claims

### Claim 1

A PDM (pulse density modulation) signal energy detection circuit, comprising:
a multiple-stage switched-capacitor filter circuit having multiple filter stages for receiving a PDM digital input signal, the multiple-stage switched-capacitor filter circuit producing a non-inverting analog output signal and an inverting analog output signal based on the PDM digital input signal;
a comparator circuit for receiving the non-inverting analog output signal and the inverting analog output signal from the multiple-stage switched-capacitor filter circuit, the comparator circuit producing a pulsed signal when a magnitude of the non-inverting analog output signal or the inverting analog output signal exceeds a pre-set threshold; and
a counter circuit receiving the pulsed signal from the comparator circuit and producing an energy detection signal when a number of consecutive pulsed signals exceeds a pre-set count;
wherein the filter stages each comprises of a single MOSFET gain stage, a MOSFET current source carrying a current Ibias and a switched capacitor network, the single MOSFET gain stage being biased at a current Ibias and having an average voltage of Vnbias at a drain and gate connection, wherein Vnbias is a bias voltage derived from an external MOSFET gate voltage having drain and gate tied together and biased at a current Ibias.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the multiple-stage switched-capacitor filter circuit comprises:
an input sampling filter stage; and
an output filter stage.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the input sampling filter stage is configured to sample an input voltage Vnbias through switches controlled by the PDM digital input signal; and
wherein the input sampling filter stage is configured to produce an output voltage of
Vnbias
±
(
2
×
Dp
-
50
100
)
×
Vnbias
,
where Dp is a density of pulses of the PDM digital input signal, expressed as a percentage.

### Claim 4 (depends on 2)

The circuit of claim 2, wherein the input sampling filter stage comprises:
a feedback capacitor coupling a drain and a gate of the single MOSFET gain stage;
a switching capacitor coupled to the feedback capacitor;
a sampling capacitor coupled to the switching capacitor and the feedback capacitor; and
a plurality of switches for coupling the sampling capacitor, the switching capacitor, and the feedback capacitor;
wherein the sampling capacitor is configured to receive a PDM (pulse density modulation) digital data signal; and
wherein the input sampling filter stage is configured to produce an analog signal with a magnitude that is based on a density of the PDM digital input signal.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the input sampling filter stage is configured to be a low-pass filter with a cut-off frequency of:
Fc
=
1
/
(
2
⁢
π
×
Cfb
×
Tdmclk
Csw
)
where:
Cfb is the capacitance of the feedback capacitor;
Csw is the capacitance of the switching capacitor; and
Tdmclk is a clock period of the PDM digital input signal.

### Claim 6 (depends on 2)

The circuit of claim 2, wherein the output filter stage comprises:
a first switched capacitor output filter; and
a second switched capacitor output filter;
wherein the output filter stage is configured to receive an input signal from a previous stage and to produce the non-inverter output analog signal and the inverting analog output signal.

### Claim 7 (depends on 2)

The circuit of claim 2, further comprising one or more intermediate filter stages coupled between the input sampling filter stage and the output filter stage, wherein each of the intermediate filter stages is a switched-capacitor low-pass filter.

### Claim 8 (depends on 7)

The circuit of claim 7, wherein each of the one or more intermediate filter stages comprises:
a feedback capacitor coupling a drain and a gate of the single MOSFET gain stage;
a switching capacitor coupled to the feedback capacitor;
a sampling capacitor coupled to the switching capacitor and the feedback capacitor; and
a plurality of switches for coupling the sampling capacitor, the switching capacitor, and the feedback capacitor.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein each of the one or more intermediate filter stages is configured to be a low-pass filter with a cut-off frequency of:
Fc
=
1
/
(
2
⁢
π
×
Cfb
×
Tdmclk
Csw
)
where:
Cfb is the capacitance of the feedback capacitor;
Csw is the capacitance of the switching capacitor; and
Tdmclk is a clock period of the PDM digital input signal.

### Claim 10 (depends on 1)

The circuit of claim 1, wherein each filter stage of the multiple-stage switched-capacitor filter circuit comprises:
a feedback capacitor coupling a drain and a gate of the single MOSFET gain stage;
a switching capacitor coupled to the feedback capacitor;
a sampling capacitor coupled to the switching capacitor and the feedback capacitor; and
a plurality of switches for coupling the sampling capacitor, the switching capacitor, and the feedback capacitor.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein each filter stage of the multiple-stage switched-capacitor filter circuit is configured to be a low-pass filter with a cut-off frequency of:
Fc
=
1
/
(
2
⁢
π
×
Cfb
×
Tdmclk
Csw
)
where:
Cfb is the capacitance of the feedback capacitor;
Csw is the capacitance of the switching capacitor; and
Tdmclk is a clock period of the PDM digital input signal.

### Claim 12 (depends on 1)

The circuit of claim 1, wherein the comparator circuit comprises a comparator and a latch;
wherein the comparator includes:
first and second input NMOS transistors coupled in parallel at drain terminals and source terminals, the first input NMOS transistor having a gate terminal for receiving the non-inverting output analog signal, the second input NMOS transistor having a gate terminal configured for receiving the inverting output analog signal;
a source resistor coupled to the source terminals of the first and second input NMOS transistors and providing a voltage Vres that represents a rectified signal based on the non-inverting analog output signal or the inverting analog output signal; and
a programmable resistor Rp coupled to the drain terminals of the first and second NMOS transistors; and
wherein the latch is configured to produce the pulsed signal when a magnitude of the rectified signal exceeds a threshold.

### Claim 13

A PDM (pulse density modulation) signal energy detection circuit, comprising:
a digital-to-analog converter circuit for receiving a PDM digital input signal and producing an analog output signal based on the PDM digital input signal;
a comparator circuit for receiving the analog output signal from the digital-to-analog converter circuit and producing a pulsed signal when a magnitude of the analog output signal exceeds a pre-set threshold; and
a counter circuit for receiving the pulsed signal from the comparator circuit and producing an energy detection signal when a number of consecutive pulsed signals exceed a pre-set count;
wherein the digital-to-analog converter circuit comprises a single MOSFET gain stage, a MOSFET current source carrying a current Ibias and a switched capacitor network, the single MOSFET gain stage being biased at a current Ibias and having an average voltage of Vnbias at a drain and gate connection, wherein Vnbias is a bias voltage derived from an external MOSFET gate voltage having drain and gate tied together and biased at a current Ibias.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein the digital-to-analog converter circuit is configured to sample an input voltage Vnbias through switches controlled by the PDM digital input signal; and
wherein the digital-to-analog converter circuit is configured to produce an output voltage of
Vnbias
±
(
2
×
Dp
-
50
100
)
×
Vnbias
,
where Dp is a density of pulses of the PDM digital input signal, expressed as a percentage.

### Claim 15 (depends on 13)

The circuit of claim 13, wherein the digital-to-analog converter circuit comprises a switched-capacitor circuit that includes:
an MOSFET for receiving a bias current from a current source;
a feedback capacitor coupling a drain and a gate of the MOSFET;
a switching capacitor coupled to the feedback capacitor;
a sampling capacitor coupled to the switching capacitor and the feedback capacitor; and
a plurality of switches for coupling the sampling capacitor, the switching capacitor, and the feedback capacitor;
wherein the sampling capacitor is configured to receive a PDM (pulse density modulation) digital data signal; and
wherein the digital-to-analog converter is configured to produce an analog signal with a magnitude that is based on a density of the PDM digital data signal.

### Claim 16 (depends on 15)

The circuit of claim 15, wherein the digital-to-analog converter circuit is configured to be a low-pass filter with a cut-off frequency of:
Fc
=
1
/
(
2
⁢
π
×
Cfb
×
Tdmclk
Csw
)
where:
Cfb is a capacitance of the feedback capacitor;
Csw is a capacitance of the switching capacitor; and
Tdmclk is a clock period of the PDM digital input signal.

### Claim 17 (depends on 15)

The circuit of claim 15, wherein the digital-to-analog converter circuit is configured to produce a non-inverting analog output signal and an inverting analog signal.

### Claim 18

A circuit for receiving a PDM digital input signal and producing an analog output signal based on the PDM digital input signal, comprising:
an MOSFET for receiving a bias current Ibias from a current source and having an average voltage of Vnbias at a drain and gate connection; and
a plurality of capacitors coupled to the MOSFET;
wherein the circuit is configured to sample an input voltage Vnbias through switches controlled by the PDM digital input signal, wherein Vnbias is a bias voltage derived from a gate-to-source voltage of an external MOSFET having drain and gate tied together and biased at a current Ibias; and
wherein the circuit is configured to produce an analog output voltage with a magnitude that is based on a density of the PDM digital input signal, the analog output voltage having an expression:
Vnbias
±
(
2
×
Dp
-
50
100
)
×
Vnbias
,
where Dp is a density of pulses of the PDM digital input signal, expressed in a percentage.

### Claim 19 (depends on 18)

The circuit of claim 18, further comprising:
a feedback capacitor coupling a drain and a gate of the MOSFET;
a switching capacitor coupled to the feedback capacitor;
a sampling capacitor coupled to the switching capacitor and the feedback capacitor;
and
a plurality of switches for coupling the sampling capacitor, the switching capacitor, and the feedback capacitor.

### Claim 20 (depends on 19)

The circuit claim 19, wherein the circuit is configured to be a low-pass filter with a cut-off frequency of:
Fc
=
1
/
(
2
⁢
π
×
Cfb
×
Tdmclk
Csw
)
where:
Cfb is the capacitance of the feedback capacitor;
Csw is the capacitance of the switching capacitor; and
Tdmclk is a clock period of the PDM digital input signal.