# US 10,483,996 B1 · Time skew calibration of time-interleaved analog to digital converters > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,996 B1 - Document ID: US10483996B1 - Status: Granted - Kind: B1 - Application number: 15/991,539 - Filed: 2018-05-29 - Granted: 2019-11-19 - Earliest claimed: 2018-05-29 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Christophe Erdmann; Bob W. Verbruggen; Ali Boumaalif; Bruno Miguel Vaz - Web page: https://patentgrep.com/patent/US10483996B1 ## CPC - H03M 1/1033: {over the full range of the converter, e.g. for correcting differential non-linearity} - H03M 1/121: {Interleaved, i.e. using multiple converters or converter parts for one channel} - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03M 1/0624: {by synchronisation} - H03M 1/0626: {by filtering} - H03M 1/0656: {in the time domain, e.g. using intended jitter as a dither signal} - H03M 1/0836: {of phase error, e.g. jitter} - H03M 1/10: Calibration or testing - H03M 1/662: {Multiplexed conversion systems} - H03M 1/1215: {using time-division multiplexing} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency. ## Claims ### Claim 1 A clock skew calibration apparatus comprising: an array of N time-interleaved analog-to-digital converters (TIADCs) receiving an analog input signal and configured to generate a stream of originating samples in a digital format, wherein the stream rate of the generated stream is one sample per period of an overall sampling clock (sclk) having a sampling frequency fS, and wherein the TIADCs are configured to receive an array of sampling clocks each having an individual sampling frequency of substantially fS/N; and, a time skew extractor circuit comprising: a summer circuit operatively coupled to receive the generated sample stream and a stream of delayed samples of the generated sample stream, wherein the summer circuit is configured to sum two consecutive samples from the generated sample stream; and, a first absolute value circuit operatively coupled to the summer circuit, wherein the first absolute value circuit is operatively coupled to produce an array of clock error signals as a function of the summed consecutive samples of the generated sample stream. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first absolute value circuit further comprises a bit manipulator coupled to an output of the summer circuit for generating initial absolute values of the output of the summer circuit. ### Claim 3 (depends on 1) The apparatus of claim 1, the summer circuit further comprising a first input coupled to the generated sample stream, and a flip flop having an input coupled to receive the generated sample stream, wherein the summer circuit further comprises an output of the flip flop coupled to a second input of the summer circuit. ### Claim 4 (depends on 3) The apparatus of claim 3, the time skew extractor circuit further comprising a subtractor circuit operatively coupled to receive the generated sample stream at a first input and configured to subtract two consecutive samples from the generated sample stream. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the time skew extractor circuit further comprises the output of the flip flop coupled to a second input of the subtractor circuit. ### Claim 6 (depends on 5) The apparatus of claim 5, further comprising a second absolute value circuit operatively coupled to an output of the subtractor circuit. ### Claim 7 (depends on 6) The apparatus of claim 6, the time skew extractor circuit further comprising a combiner circuit operatively coupled to receive the respective outputs of the first and second absolute value circuits, wherein the time skew extractor circuit is operative to produce an array of clock error signals as a function of the combined absolute value outputs. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the combiner circuit further comprises a difference generator, wherein the time skew extractor circuit is operative to produce an array of clock error signals as a function of the difference of the absolute value outputs. ### Claim 9 (depends on 7) The apparatus of claim 7, further comprising time skew correction generator adapted to receive the array of clock error signals and to produce the array of sampling clocks. ### Claim 10 A method to calibrate clock skew, the method comprising: receiving, with an array of N time-interleaved analog-to-digital converters (TIADCs), an analog input signal; generating, from the received analog input signal, a stream of originating samples in a digital format, wherein the stream rate of the generated stream is one sample per period of an overall sampling clock (sclk) having a sampling frequency fS, and wherein the TIADCs are configured to receive an array of sampling clocks each having an individual sampling frequency of substantially fS/N; and, providing a time skew extractor circuit comprising a summer circuit operatively coupled to receive the generated sample stream and a stream of delayed samples of the generated sample stream; summing, with the summer circuit, consecutive samples from the generated sample stream, and, producing, with a first absolute value circuit operatively coupled to the summer circuit, an array of clock error signals as a function of the summed consecutive samples of the generated sample stream. ### Claim 11 (depends on 10) The method of claim 10, wherein the first absolute value circuit further comprises a bit manipulator coupled to an output of the summer circuit, and the method further comprises generating initial absolute values of the output of the summer circuit. ### Claim 12 (depends on 10) The method of claim 10, wherein the summer circuit further comprises a first input coupled to the generated sample stream, and a flip flop having an input coupled to receive the generated sample stream, wherein the summer circuit further comprises an output of the flip flop coupled to a second input of the summer circuit. ### Claim 13 (depends on 12) The method of claim 12, wherein the time skew extractor circuit further comprises a subtractor circuit operatively coupled to receive the generated sample stream at a first input, and the method further comprises subtracting, with the subtractor circuit, two consecutive samples from the generated sample stream. ### Claim 14 (depends on 13) The method of claim 13, wherein the time skew extractor circuit further comprises the output of the flip flop coupled to a second input of the subtractor circuit. ### Claim 15 (depends on 14) The method of claim 14, further comprising providing a second absolute value circuit operatively coupled to an output of the subtractor circuit. ### Claim 16 A clock skew calibration apparatus comprising: an array of N time-interleaved analog-to-digital converters (TIADCs) receiving an analog input signal and configured to generate a stream of originating samples in a digital format, wherein the stream rate of the generated stream is one sample per period of an overall sampling clock (sclk) having a sampling frequency fS, and wherein the TIADCs are configured to receive an array of sampling clocks each having an individual sampling frequency of substantially fS/N; and, a sign changer circuit configured to receive the stream of originating samples and to generate a stream of mixed samples at the sampling frequency fS, wherein the stream of mixed samples alternates between a sample that is a direct copy of the originating sample and a sign changed copy of the originating sample, wherein a time skew extractor is adapted to receive the stream of mixed samples and to produce an array of clock error signals as a function of the stream of mixed samples, and, wherein a time skew correction circuit is adapted to receive the array of clock error signals and to produce the array of sampling clocks. ### Claim 17 (depends on 16) The apparatus of claim 16, further comprising a selector configured to receive the stream of originating samples and to receive the stream of mixed samples and configured to send a selected one of the received sample streams to the time skew extractor in response to a selection control signal. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the selector is configured to select between the received sample streams as a function of a frequency of the analog input signal relative to a Nyquist frequency associated with the sampling frequency fs.