Calibration of radix errors using Least-Significant-Bit (LSB) averaging in a Successive-Approximation Register Analog-Digital Converter (SAR-ADC) during a fully self-calibrating routine

A radix error calibrating method for calibrating a mixed-signal converter, the method comprising:

• loading a Look-Up Table (LUT) with ideal radixes for capacitors having an ideal radix that is less than a target radix, the capacitors being in a capacitor array of the capacitors;
• (c) clearing a test accumulator;
• driving a common-mode voltage onto outer terminals of all capacitors having an ideal radix above the target radix;
• (b) driving a reference voltage to an outer terminal of an upper capacitor having the target radix;
• driving ground to an outer terminal of a lower capacitor having the target radix;
• driving a Successive-Approximation Register (SAR) search sequence of voltages onto outer terminals of capacitors having an ideal radix less than the target radix and examining a comparator output of a comparator having inputs connected to inner terminals of the capacitors to determine when to set or clear binary bits in a SAR value;
• clearing a Least-Significant-Bit (LSB) accumulator;
• driving a common-mode voltage onto outer terminals of all LSB averaging capacitors in an LSB averaging array, each LSB averaging capacitor having an ideal radix that is no more than double a LSB radix, the LSB radix being for a LSB capacitor in the array of capacitor;
• (a) driving the reference voltage to an outer terminal of a lower LSB capacitor in the LSB averaging array;
• driving ground to an outer terminal of an upper LSB capacitor in the LSB averaging array;
• examining the comparator output and incrementing the LSB accumulator when the comparator output is positive, and decrementing the LSB accumulator when the comparator output is negative;
• driving the reference voltage to the outer terminal of the upper LSB capacitor and driving ground to the outer terminal of the lower LSB capacitor when the comparator output is negative;
• repeating from (a) for other LSB averaging capacitors until all LSB capacitors have been evaluated;
• adding the LSB accumulator to the SAR value to generate a LSB-corrected SAR value;
• reading the LUT for radixes corresponding to all 1 bits in the LSB-corrected SAR value, and summing the radixes for all 1 bits to generate a test weight;
• adding the test weight to the test accumulator;
• repeating from (b) until N test weights have been accumulated into the test accumulator, and dividing the test accumulator by N to generate a digital average test weight;
• wherein N is an integer of at least 4;
• storing the digital average test weight into the LUT as the radix for the target radix;
• and
• moving the target radix to a next most-significant radix for capacitors in the capacitor array and repeating from (c) to store the digital average test weight into the LUT as the radix for the next most-significant radix until a Most-Significant-Bit (MSB) radix has been stored in the LUT.

A self-calibrating Analog-to-Digital Converter (ADC) comprising:

• a capacitor array having capacitors connected to a summing line, the capacitors having a plurality of design sizes that are multiples of a Least-Significant-Bit (LSB) design size, an ideal radix being a function of a ratio of a design size to the LSB design size;
• a comparator receiving the summing line on a comparator input and generating a comparator output;
• a Successive-Approximation Register (SAR) for applying a SAR search sequence of binary bits to terminals of the capacitors in the capacitor array;
• a Look-Up Table (LUT) for storing radixes of capacitors in the capacitor array, the LUT storing the ideal radix for lower-significance capacitors in the capacitor array wherein the ideal radix is below a threshold radix, and for storing an actual measured radix for higher-significance capacitors in the capacitor array wherein the ideal radix is above a threshold radix;
• an LSB averaging array of LSB averaging capacitors having a design size no more than twice the LSB design size, the LSB averaging capacitors connected to the summing line;
• a calibration sequencer that activates the SAR to apply the SAR search sequence to capacitors having ideal radixes below a target radix, and for successively setting or clearing binary bits in the SAR in response to a polarity of the comparator output to generate a SAR code;
• a LSB averager that applies test voltages to terminals of the LSB averaging capacitors and increments or decrements a LSB of the SAR code in response to the comparator output to generate a corrected SAR code;
• a digital averager that activates the calibration sequencer to repeat the SAR search sequence and to activate the LSB averager to repeatedly generate corrected SAR codes that are averaged together to generate an averaged corrected SAR code;
• and
• a summer for reading radixes from the LUT and summing together radixes corresponding to all 1 bits in the averaged corrected SAR code to generate an actual measured radix that is written into the LUT for the capacitor having the target radix;
• the calibration sequencer selecting a next-most-significant radix to the target radix as a new target radix and repeating the SAR search sequence for a new target radix to generate an actual measured radix for the new target radix for storage in the LUT,
• whereby actual measured radixes are generated from the SAR search sequence that is corrected by LSB averaging and then digital averaged to reduce errors.