# US 10,483,993 B1 · Residue amplifier

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- Number: US 10,483,993 B1
- Document ID: US10483993B1
- Status: Granted
- Kind: B1
- Application number: 16/234,648
- Filed: 2018-12-28
- Granted: 2019-11-19
- Earliest claimed: 2018-12-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Raghu Nandan Srinivasa; Srinivas Bangalore Seshadri; Sabu Paul
- Web page: https://patentgrep.com/patent/US10483993B1

## CPC

- H03M 1/0604: {at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)}
- H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements
- H03F 3/45246: {Folded cascode stages}
- H03F 3/45269: {Complementary non-cross coupled types}
- H03F 3/45273: {Mirror types}
- H03F 3/45632: {in differential amplifiers with FET transistors as the active amplifying circuit (H03F3/4578 takes precedence)}
- H03F 3/4565: {Controlling the common source circuit of the differential amplifier}
- H03M 1/0607: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295)}
- H03F 2203/45461: the CSC comprising one or more switched capacitors
- H03M 1/167: {all stages comprising simultaneous converters (H03M1/165 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS

## Abstract

A pipelined analog-to-digital converter (ADC) and a residue amplifier used in the ADC. An ADC includes a capacitive digital-to-analog converter (CDAC), a residue amplifier, and a switched capacitor circuit. The residue amplifier is coupled to the CDAC. The residue amplifier includes a first complementary transistor pair and a first tail current circuit. The first complementary transistor pair is coupled to a first output of the CDAC, and includes a high-side transistor and a low-side transistor. The first tail current circuit is coupled to the high side transistor. The switched capacitor circuit is coupled to inputs of the CDAC and to the first tail current circuit. The switched capacitor circuit is configured to generate a voltage to bias the first tail current circuit with compensation for common mode voltage at the inputs of the CDAC.

## Claims

### Claim 1

An analog-to-digital converter (ADC), comprising:
a capacitive digital-to-analog converter (CDAC);
a residue amplifier coupled to the CDAC, and comprising:
a first complementary transistor pair coupled to a first output of the CDAC, and comprising:
a high-side transistor; and
a low-side transistor; and
a first tail current circuit coupled to the high side transistor;
a switched capacitor circuit coupled to inputs of the CDAC and the first tail current circuit, and configured to:
generate a voltage to bias the first tail current circuit; and
compensate for common mode voltage at the inputs of the CDAC.

### Claim 2 (depends on 1)

The ADC of claim 1, wherein the residue amplifier further comprises a second tail current circuit coupled to the low side transistor and the switched capacitor circuit, and biased by the voltage generated by the switched capacitor circuit.

### Claim 3 (depends on 2)

The ADC of claim 2, wherein the residue amplifier further comprises a second complementary transistor pair coupled to a second output of the CDAC, and comprising:
a high-side transistor biased by the first tail current circuit; and
a low-side transistor biased by the second tail current circuit.

### Claim 4 (depends on 1)

The ADC of claim 1, wherein the switched capacitor circuit comprises:
a first plurality of sampling capacitors, and
a first plurality of sampling switches;
wherein each of the sampling capacitors is coupled to a first input of the CDAC via a different one of the sampling switches.

### Claim 5 (depends on 4)

The ADC of claim 4, wherein the switched capacitor circuit comprises:
a hold switch coupled to the sampling capacitors; and
a hold capacitor coupled to the hold switch, wherein the voltage is generated on a top plate of the hold capacitor.

### Claim 6 (depends on 5)

The ADC of claim 5, wherein the switched capacitor circuit comprises:
a second plurality of sampling capacitors, and
a second plurality of sampling switches;
wherein each of the sampling capacitors of the second plurality of sampling capacitors is coupled to a second input of the CDAC via a different one of the sampling switches of the second plurality of sampling switches.

### Claim 7 (depends on 6)

The ADC of claim 6, wherein the switched capacitor circuit comprises a top plate common mode switch configured to switchably couple a top plate of each of the sampling capacitors of the switched capacitor circuit to a top plate of each of the sampling capacitors of the CDAC.

### Claim 8

A residue amplifier, comprising:
a preamplifier, comprising:
a first transistor;
a second transistor comprising:
a first terminal coupled to a first terminal of the first transistor; and
a second terminal coupled to a second terminal of the first transistor;
a third transistor comprising a first terminal coupled to a third terminal of the first transistor;
a fourth transistor comprising:
a first terminal coupled to a second terminal of the third transistor;
a second terminal coupled to a third terminal of the third transistor; and
a third terminal coupled to a third terminal of the second transistor;
a first tail current circuit coupled to the first terminal of the third transistor and the third terminal of the first transistor; and
a switched capacitor circuit comprising a hold capacitor, wherein a top plate of the hold capacitor is coupled to a terminal of the first tail current circuit.

### Claim 9 (depends on 8)

The residue amplifier of claim 8, wherein the preamplifier comprises a second tail current circuit coupled to the third terminal of the second transistor and the third terminal of the fourth transistor; wherein the top plate of the hold capacitor is coupled to a terminal of the second tail current circuit.

### Claim 10 (depends on 9)

The residue amplifier of claim 9, wherein the second bias circuit comprises:
a fifth transistor comprising a first terminal coupled to the third terminal of the second transistor and the third terminal of the fourth transistor;
a sixth transistor comprising:
a first terminal coupled to a second terminal of the first fifth transistor; and
a second terminal coupled to a third terminal of the fifth transistor; and
a seventh transistor comprising:
a first terminal coupled to a third terminal of the sixth transistor;
a second terminal coupled to the second terminal of the sixth transistor and the third terminal of the fifth transistor; and
a third terminal coupled to the top plate of the hold capacitor.

### Claim 11 (depends on 8)

The residue amplifier of claim 8, wherein the first bias circuit comprises:
a fifth transistor comprising a first terminal coupled to the first terminal of the third transistor and the third terminal of the first transistor;
a sixth transistor comprising:
a first terminal coupled to a second terminal of the fifth transistor; and
a second terminal coupled to a third terminal of the fifth transistor; and
a seventh transistor comprising:
a first terminal coupled to a third terminal of the sixth transistor;
a second terminal coupled to the second terminal of the sixth transistor and the third terminal of the fifth transistor; and
a third terminal coupled to the top plate of the hold capacitor.

### Claim 12 (depends on 8)

The residue amplifier of claim 8, wherein the switched capacitor circuit comprises:
a first input terminal;
a first plurality of sampling switches, each of the sampling switches comprising a first terminal coupled to the first input terminal; and
a first plurality of sampling capacitors, each of the sampling capacitors comprising a bottom plate coupled to a second terminal of one of the sampling switches.

### Claim 13 (depends on 12)

The residue amplifier of claim 12, wherein the switched capacitor circuit comprises:
a second input terminal;
a second plurality of sampling switches, each of the sampling switches of the second plurality of sampling switches comprising a first terminal coupled to the second input terminal; and
a second plurality of sampling capacitors, each of the sampling capacitors of the second plurality of sampling capacitors comprising a bottom plate coupled to a second terminal of one of the sampling switches of the second plurality of sampling switches.

### Claim 14 (depends on 13)

The residue amplifier of claim 13, wherein the switched capacitor circuit comprises a hold switch comprising:
a first terminal coupled to a top plate of the each of the sampling capacitors of the first plurality of sampling capacitors and to a top plate of the each of the sampling capacitors of the second plurality of sampling capacitors; and
a second terminal coupled to the top plate of the hold capacitor.

### Claim 15 (depends on 13)

The residue amplifier of claim 13, wherein the switched capacitor circuit comprises a top plate common mode switch comprising a first terminal coupled to the first terminal of the hold switch.

### Claim 16

A residue amplifier, comprising:
a preamplifier comprising:
a first input terminal for connection to a first output of a capacitive digital-to-analog converter (CDAC);
a second input terminal for connection to a second output of the CDAC;
a first complementary transistor pair coupled to the first input terminal;
a second complementary transistor pair coupled to the second input terminal;
a first tail current circuit coupled to, and configured to provide a first bias current to, the first complementary transistor pair and the second complementary transistor pair;
a second tail current circuit coupled to, and configured to provide a second bias current to, the first complementary transistor pair and the second complementary transistor pair; and
a switched capacitor circuit coupled to the first tail current circuit and the second tail current circuit, and configured to provide to the first tail current circuit and the second tail current circuit a bias voltage that is a function of top plate common mode voltage provided to the CDAC and common mode voltage of input signal provided to the CDAC for digitization.

### Claim 17 (depends on 16)

The residue amplifier of claim 16, wherein the switched capacitor circuit comprises:
a first plurality of sampling capacitors,
a first plurality of sampling switches; wherein each of the sampling capacitors is coupled to a first input of the CDAC via a different one of the sampling switches;
a second plurality of sampling capacitors, and
a second plurality of sampling switches;
wherein each of the sampling capacitors of the second plurality of sampling capacitors is coupled to a second input of the CDAC via a different one of the sampling switches of the second plurality of sampling switches.

### Claim 18 (depends on 17)

The residue amplifier of claim 17, wherein the switched capacitor circuit comprises a top plate common mode switch configured to switchably couple a top plate of each of the sampling capacitors of the switched capacitor circuit to a top plate of each sampling capacitor of the CDAC.

### Claim 19 (depends on 18)

The residue amplifier of claim 18, wherein the switched capacitor circuit comprises:
a hold switch coupled to the sampling capacitors; and
a hold capacitor coupled to the hold switch.

### Claim 20 (depends on 19)

The residue amplifier of claim 19, wherein the bias voltage is generated on a top plate of the hold capacitor.