# US 10,483,989 B2 · Phase-locked loop, phase-locking method, and communication unit

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- Number: US 10,483,989 B2
- Document ID: US10483989B2
- Status: Granted
- Kind: B2
- Application number: 15/751,094
- Filed: 2016-08-15
- Published: 2018-08-16
- Granted: 2019-11-19
- Earliest claimed: 2015-09-11
- Assignees: Sony Semiconductor Solutions Corporation
- Applicants: Sony Semiconductor Solutions Corporation
- Inventors: Takashi Masuda
- Web page: https://patentgrep.com/patent/US10483989B2

## CPC

- H03L 7/083: the reference signal being additionally directly applied to the generator
- H03L 7/07: using several loops, e.g. for redundant clock signal generation
- H03L 7/08: Details of the phase-locked loop
- H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/0997: {Controlling the number of delay elements connected in series in the ring oscillator}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A phase-locked loop of the disclosure includes a detector, an oscillator, an adjuster, and a controller. The detector detects a transition of an input clock signal. The oscillator generates a clock signal having a frequency corresponding to a first control signal, and changes a phase of the clock signal on a basis of a detection result in the detector. The adjuster adjusts a phase difference between a phase of the input clock signal and the phase of the clock signal depending on a second control signal. The controller compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on a basis of a result of the comparison.

## Claims

### Claim 1

A phase-locked loop comprising:
a detector that detects at least transition of an input clock signal;
an oscillator that generates a clock signal having a frequency corresponding to a first control signal, and changes a phase of the clock signal on a basis of a detection result in the detector, wherein the basic of the detection result comprises a pulse signal;
an adjuster that adjusts a phase difference between a phase of the input clock signal and the phase of the clock signal depending on a second control signal; and
a controller that compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on a basis of a result of the comparison.

### Claim 2 (depends on 1)

The phase-locked loop according to claim 1, further comprising a frequency divider that divides a frequency of the clock signal, wherein
the controller compares the phase of the input clock signal and the phase of the clock signal of which frequency is divided by the frequency divider.

### Claim 3 (depends on 1)

The phase-locked loop according to claim 1, wherein
the adjuster includes a second delay section that delays the input clock signal by an amount of delay corresponding to the second control signal, and
the detector detects the at least transition of the input clock signal delayed by the second delay section.

### Claim 4 (depends on 1)

The phase-locked loop according to claim 1, wherein
the adjuster includes a third delay section that delays the clock signal by an amount of delay corresponding to the second control signal, and
the controller compares the phase of the input clock signal and the phase of the clock signal delayed by the third delay section.

### Claim 5 (depends on 1)

The phase-locked loop according to claim 1, further comprising a frequency divider that divides a frequency of the clock signal, wherein
the adjuster includes a fourth delay section that delays the clock signal of which frequency is divided by the frequency divider, by an amount of delay corresponding to the second control signal, and
the controller compares the phase of the input clock signal and the phase of the clock signal delayed by the fourth delay section.