# US 10,483,988 B1 · Synchronization circuit and method relating to the synchronization circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,988 B1 - Document ID: US10483988B1 - Status: Granted - Kind: B1 - Application number: 16/224,603 - Filed: 2018-12-18 - Published: 2019-11-28 - Granted: 2019-11-19 - Earliest claimed: 2018-05-24 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Tae Pyeong Kim - Web page: https://patentgrep.com/patent/US10483988B1 ## CPC - H03L 7/0818: {the controlled phase shifter comprising coarse and fine delay or phase-shifting means} - G11C 7/1066: {Output synchronization} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 29/023: {in clock generator or timing circuitry} - G11C 29/028: {with adaption or trimming of parameters} - H03L 7/0814: {the phase shifting device being digitally controlled} - H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input} - G11C 2207/2254: Calibration - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A synchronization circuit may include: a variable delay circuit configured to delay a first clock signal by a varied delay time according to delay control signals, and configured to output a delayed signal of the variable delay circuit as a second clock signal; a phase detector configured to generate a phase detection signal by detecting a phase difference between the first and second clock signals; and a delay control circuit configured to perform a phase unstable period detection operation according to the phase detection signal, and configured to perform a delay skip operation to adjust the delay control signals such that a phase unstable period, detected in the phase unstable period detection operation, is skipped in a delay time tuning operation. ## Claims ### Claim 1 A synchronization circuit comprising: a variable delay circuit configured to delay a first clock signal by a varied delay time according to delay control signals, and configured to output a delayed signal of the variable delay circuit as a second clock signal; a phase detector configured to generate a phase detection signal by detecting a phase difference between the first and second clock signals; and a delay control circuit configured to perform a phase unstable period detection operation according to the phase detection signal, and configured to perform a delay skip operation to adjust the delay control signals according to skip period information such that a phase unstable period, detected in the phase unstable period detection operation, is skipped in a delay time tuning operation, wherein the delay control circuit includes a skip period information generation circuit configured to generate the skip period information by performing the phase unstable period detection operation according to the phase detection signal. ### Claim 2 (depends on 1) The synchronization circuit according to claim 1, wherein the variable delay circuit comprises: a first delay circuit comprising first unit delays; and a second delay circuit comprising second unit delays configured to have a smaller delay time than the first unit delays of the first delay circuit. ### Claim 3 (depends on 2) The synchronization circuit according to claim 2, wherein the first delay circuit comprises: the first unit delays configured to sequentially delay the first clock signal and to output delayed signals of the first unit delays; and a multiplexer configured to generate an output signal by selecting any one of the delayed signals of the first unit delays according to a first delay control signal among the delay control signals. ### Claim 4 (depends on 2) The synchronization circuit according to claim 2, wherein the second delay circuit comprises: the second unit delays configured to sequentially delay the output signal of the first delay circuit and to output delayed signals of the second unit delays; and a multiplexer configured to generate an output signal by selecting any one of the delayed signals of the second unit delays according to a second delay control signal among the delay control signals. ### Claim 5 (depends on 1) The synchronization circuit according to claim 1, wherein the delay control circuit performs the phase unstable period detection operation when the current operation state of the synchronization circuit is a power-up sequence. ### Claim 6 (depends on 5) The synchronization circuit according to claim 5, wherein the delay control circuit recognizes the power-up sequence according to edge information of a power-up signal. ### Claim 7 (depends on 5) The synchronization circuit according to claim 5, wherein when the current operation state of the synchronization circuit is not the power-up sequence, the delay control circuit performs the delay skip operation using a result of the phase unstable period detection operation performed prior to the performance of the delay skip operation. ### Claim 8 (depends on 1) The synchronization circuit according to claim 1, wherein the delay control circuit performs the phase unstable period detection operation by performing a plurality of phase detection operation sets, wherein the plurality of phase detection operation sets are performed by differently setting the varied delay time of the variable delay circuit for each of the phase detection operation sets, and wherein each of the phase detection operation sets includes a plurality of phase detections which are performed while the varied delay time of the variable delay circuit is fixed. ### Claim 9 (depends on 8) The synchronization circuit according to claim 8, wherein when any one result of the plurality of phase detections has a different value from any other result of the plurality of phase detections, the delay control circuit detects the corresponding phase detection operation set as a phase unstable period. ### Claim 10 (depends on 1) The synchronization circuit according to claim 1, wherein the skip period information generation circuit comprises: a shift register configured to sequentially shift the phase detection signal and to output the shifted signals; a logic gate configured to perform a logic operation on the output signals of the shift register, and configured to output the logic operation result; a counter configured to generate a phase unstable period count signal by counting the output signal of the logic gate; and a register configured to store the phase unstable period count signal. ### Claim 11 A synchronization circuit comprising: a first delay circuit configured to delay a first clock signal by a varied delay time according to a first delay control signal, and configured to output a delayed signal of the first delay circuit; a second delay circuit configured to delay the output signal of the first delay circuit by a varied delay time according to a second delay control signal, and configured to output a delayed signal of the second delay circuit as a second clock signal; a phase detector configured to generate a phase detection signal by detecting a phase difference between the first and second clock signals; a skip period information generation circuit configured to generate skip period information by performing a phase unstable period detection operation according to the phase detection signal; and a delay control signal generation circuit configured to adjust the second delay control signal according to the skip period information, such that a phase unstable period, detected in the phase unstable period detection operation, is skipped in a delay time tuning operation. ### Claim 12 (depends on 11) The synchronization circuit according to claim 11, wherein second unit delays of the second delay circuit are configured to have a smaller delay time than first unit delays of the first delay circuit. ### Claim 13 (depends on 11) The synchronization circuit according to claim 11, wherein the first delay circuit comprises: first unit delays configured to sequentially delay the first clock signal and to output delayed signals of the first unit delays; and a multiplexer configured to generate an output signal by selecting any one of the delayed signals of the first unit delays according to the first delay control signal. ### Claim 14 (depends on 11) The synchronization circuit according to claim 11, wherein the second delay circuit comprises: second unit delays configured to sequentially delay the output signal of the first delay circuit and to output delayed signals of the second unit delays; and a multiplexer configured to generate an output signal by selecting any one of the delayed signals of the second unit delays according to the second delay control signal. ### Claim 15 (depends on 11) The synchronization circuit according to claim 11, wherein the skip period information generation circuit comprises: a shift register configured to sequentially shift the phase detection signal and to output the shifted signals; a logic gate configured to perform a logic operation on the output signals of the shift register, and configured to output the logic operation result; a counter configured to generate a phase unstable period count signal by counting the output signal of the logic gate; and a register configured to store the phase unstable period count signal, and configured to output the stored signal as the skip period information. ### Claim 16 (depends on 15) The synchronization circuit according to claim 15, wherein the output signals of the shift register, the phase unstable period count signal, and the skip period information are reset according to a power-up signal. ### Claim 17 (depends on 11) The synchronization circuit according to claim 11, wherein the delay control signal generation circuit performs the phase unstable period detection operation when the current operation state of the synchronization circuit is a power-up sequence. ### Claim 18 (depends on 17) The synchronization circuit according to claim 17, wherein the delay control signal generation circuit recognizes the power-up sequence according to edge information of a power-up signal. ### Claim 19 (depends on 17) The synchronization circuit according to claim 17, wherein when the current operation state of the synchronization circuit is not the power-up sequence, the delay control signal generation circuit adds the skip period information value to the initial value of the second delay control signal. ### Claim 20 (depends on 11) The synchronization circuit according to claim 11, wherein the skip period information generation circuit performs the phase unstable period detection operation by performing a plurality of phase detection operation sets, wherein the plurality of phase detection operation sets are performed by differently setting the varied delay time of the second delay circuit for each of the phase detection operation sets, and wherein each of the phase detection operation sets includes a plurality of phase detections which are performed while the varied delay time of the second delay circuit is fixed. ### Claim 21 (depends on 20) The synchronization circuit according to claim 20, wherein when any one result of the plurality of phase detections has a different value from any other result of the plurality of phase detections, the skip period information generation circuit detects the corresponding phase detection operation set as a phase unstable period. ### Claim 22 A method for operating a synchronization circuit, the method comprising: determining whether the current operation state of the synchronization circuit is a power-up sequence; performing a phase unstable period detection operation by controlling a second delay circuit when the current operation state is the power-up sequence; storing the number of unit delays of the second delay circuit corresponding to a phase unstable period, detected in the phase unstable period detection operation, as skip period information; and performing a delay time tuning operation by controlling a first delay circuit and the second delay circuit when the current operation state is not the power-up sequence, wherein the second delay circuit is controlled according to the skip period information such that the phase unstable period is skipped when performing the delay time tuning operation. ### Claim 23 (depends on 22) The method of claim 22, wherein the unit delays of the second delay circuit are configured to have a smaller delay time than unit delays of the first delay circuit. ### Claim 24 (depends on 22) The method of claim 22, wherein the performing of the phase unstable period detection operation includes performing a plurality of phase detection operation sets, wherein the plurality of phase detection operation sets are performed by differently setting a delay time of the second delay circuit for each of the phase detection operation sets, and wherein each of the phase detection operation sets includes a plurality of phase detections which are performed while the delay time of the second delay circuit is fixed. ### Claim 25 (depends on 24) The method of claim 24, wherein when any one result of the plurality of phase detections has a different value from any other result of the plurality of phase detections, the corresponding phase detection operation set is detected as a phase unstable period.