# US 10,483,983 B2 · Clock generating circuit and signal processing device

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- Number: US 10,483,983 B2
- Document ID: US10483983B2
- Status: Granted
- Kind: B2
- Application number: 15/683,788
- Filed: 2017-08-23
- Published: 2018-03-15
- Granted: 2019-11-19
- Earliest claimed: 2016-09-09
- Assignees: Nihon Dempa Kogyo Co., Ltd.
- Applicants: Nihon Dempa Kogyo Co., Ltd.
- Inventors: Tomoya Yorita; Shoichi Tsuchiya; Yasuo Kitayama
- Web page: https://patentgrep.com/patent/US10483983B2

## CPC

- H03L 1/027: {by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/subtract logic circuit (H03L1/023, H03L1/026 take precedence)}
- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- H03K 21/10: comprising logic circuits
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A clock generating circuit includes a dividing unit and a distribution unit. The dividing unit divides a reference clock to generate a divided clock, and the divided clock has a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more. The distribution unit distributes the reference clock to a first route and a second route, the first route includes an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, and the second route includes the dividing unit. The dividing unit includes one or more amplifiers, one or more dividing circuits, and a correction circuit. The correction circuit is disposed between the amplifier and the dividing circuit, and the correction circuit corrects a level of an input clock input to the dividing circuit.

## Claims

### Claim 1

A clock generating circuit, comprising:
a dividing unit that divides a reference clock to generate a divided clock, the divided clock having a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more; and
a distribution unit that distributes the reference clock to a first route and a second route, the first route including an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, the second route including the dividing unit,
wherein the dividing unit comprises:
one or more amplifiers;
one or more dividing circuits; and
a correction circuit, disposed between the amplifier and the dividing circuit, the correction circuit corrects a level of an input clock input to the dividing circuit.

### Claim 2 (depends on 1)

The clock generating circuit according to claim 1, wherein
the correction circuit comprises a thermistor having a resistance value variable depending on temperature.

### Claim 3 (depends on 1)

The clock generating circuit according to claim 1, wherein
the correction circuit corrects the level of the input clock such that the input clock has a waveform of a rectangular wave.

### Claim 4 (depends on 1)

The clock generating circuit according to claim 1, wherein
the dividing unit comprises:
a plurality of the dividing circuits connected in cascade; and
the correction circuits located at former parts of the respective plurality of the dividing circuits, and the correction circuits having identical properties.

### Claim 5

A signal processing device, comprising:
a dividing unit that divides a reference clock to generate a divided clock, the divided clock having a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more;
a distribution unit that distributes the reference clock to a first route and a second route, the first route including an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, the second route including the dividing unit; and
an analog/digital converter that performs an analog/digital conversion on a signal with a frequency between the frequency of the reference clock and the frequency of the divided clock based on the reference clock and the divided clock,
wherein the dividing unit comprises:
one or more amplifiers;
one or more dividing circuits; and
a correction circuit, disposed between the amplifier and the dividing circuit, the correction circuit corrects a level of an input clock input to the dividing circuit.