# US 10,483,982 B2 · Frequency synthesizer with tunable accuracy > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,982 B2 - Document ID: US10483982B2 - Status: Granted - Kind: B2 - Application number: 16/139,340 - Filed: 2018-09-24 - Published: 2019-01-24 - Granted: 2019-11-19 - Earliest claimed: 2017-01-18 - Assignees: Integrated Device Technology, Inc. - Applicants: Integrated Device Technology, Inc. - Inventors: Hui Li; Teck-Chuan Ng; Stephen E. Aycock - Web page: https://patentgrep.com/patent/US10483982B2 ## CPC - H03K 21/02: Input circuits - H03M 3/39: {Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004)} - H03M 3/456: {the modulator having a first order loop filter in the feedforward path} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code. ## Claims ### Claim 1 An apparatus comprising: a first circuit configured to generate a first code by counting a number of cycles of an input clock signal during a period, wherein said period is determined by an output clock signal and a second code; a second circuit configured to generate a third code by a delta-sigma modulation of said first code, wherein said third code has fewer bits than the first code; and a third circuit configured to generate an initial frequency said output clock signal in response to said third code, wherein an accuracy of said initial frequency of said output clock signal is adjusted in response to a current value of said second code. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein said first circuit is further configured to adjust said second code to change a duration of said period. ### Claim 3 (depends on 1) The apparatus according to claim 1, wherein said first circuit is further configured to set said second code to an initial value that establishes a short duration of said period in which said frequency of said output clock signal is adjusted to a coarse accuracy. ### Claim 4 (depends on 1) The apparatus according to claim 1, wherein a coarse accuracy of said frequency of said output clock signal is achieved when said number of cycles of said input clock during said period minus an expected number falls below a threshold. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein said first circuit is further configured to set said second code to a subsequent value that establishes a long duration of said period in which said frequency of said output clock signal is adjusted to a fine accuracy. ### Claim 6 (depends on 1) The apparatus according to claim 1, wherein said first circuit is further configured to repeat a short duration of said period at most a given number of times before using a subsequent value for said second code. ### Claim 7 (depends on 1) The apparatus according to claim 1, wherein said second circuit is further configured to parse said first code into an integer value and a fractional value. ### Claim 8 (depends on 7) The apparatus according to claim 7, wherein said delta-sigma modulation is applied to said fractional value to generate a fine adjustment value. ### Claim 9 (depends on 8) The apparatus according to claim 8, wherein said third code is generated in said second circuit by adding said fine adjustment value to said integer value. ### Claim 10 (depends on 1) The apparatus according to claim 1, wherein said first circuit is further configured to vary a power consumption of said apparatus by alternately enabling and disabling said input clock signal in response to said second code. ### Claim 11 A method for frequency synthesization, comprising the steps of: generating a first code using a circuit by counting a number of cycles of an input clock signal during a period, wherein said period is determined by an output clock signal and a second code; generating a third code by a delta-sigma modulation of said first code, wherein said third code has fewer bits than the first code; and generating an initial frequency of said output clock signal in response to said third code, wherein an accuracy of said initial frequency of said output clock signal is adjusted in response to a current value of said second code. ### Claim 12 (depends on 11) The method according to claim 11, further comprising the step of: adjusting said second code to change a duration of said period. ### Claim 13 (depends on 11) The method according to claim 11, further comprising the step of: setting said second code to an initial value that establishes a short duration of said period in which said frequency of said output clock signal is adjusted to a coarse accuracy. ### Claim 14 (depends on 11) The method according to claim 11, wherein a coarse accuracy of said frequency of said output clock signal is achieved when said number of cycles of said input clock during said period minus an expected number falls below a threshold. ### Claim 15 (depends on 11) The method according to claim 11, further comprising the step of: setting said second code to a subsequent value that establishes a long duration of said period in which said frequency of said output clock signal is adjusted to a fine accuracy. ### Claim 16 (depends on 11) The method according to claim 11, further comprising the step of: repeating a short duration of said period at most a given number of times before using a subsequent value for said second code. ### Claim 17 (depends on 11) The method according to claim 11, further comprising the step of: parsing said first code into an integer value and a fractional value. ### Claim 18 (depends on 17) The method according to claim 17, wherein said delta-sigma modulation is applied to said fractional value to generate a fine adjustment value. ### Claim 19 (depends on 18) The method according to claim 18, wherein said third code is generated by adding said fine adjustment value to said integer value. ### Claim 20 (depends on 11) The method according to claim 11, further comprising the step of: alternately enabling and disabling said input clock signal in response to said second code to vary power consumption.