# US 10,483,979 B2 · Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

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- Number: US 10,483,979 B2
- Document ID: US10483979B2
- Status: Granted
- Kind: B2
- Application number: 16/262,875
- Filed: 2019-01-30
- Published: 2019-08-01
- Granted: 2019-11-19
- Earliest claimed: 2018-02-01
- Assignees: iCometrue Company Ltd.
- Applicants: iCometrue Company Ltd.
- Inventors: Mou-Shiung Lin; Jin-Yuan Lee
- Web page: https://patentgrep.com/patent/US10483979B2

## CPC

- H03K 19/1776: for memories
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/412: using field-effect transistors only
- G11C 11/419: Read-write [R-W] circuits
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0038: {Power supply circuits}
- G11C 14/009: {and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material}
- G11C 14/0081: {and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell}
- H01L 23/5386
- H01L 24/13
- H01L 24/16
- H01L 25/18
- H01L 27/224
- H01L 27/2409
- H01L 27/2436
- H01L 27/2463
- H01L 45/1233
- H01L 45/1253
- H03K 19/0948: using CMOS {or complementary insulated gate field-effect transistors}
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G11C 2213/15: Current-voltage curve
- H01L 2224/13023
- H01L 2224/13024
- H01L 2224/13147
- H01L 2224/16227
- H01L 2924/1431
- H01L 2924/1436
- H01L 2924/1437
- H01L 2924/1443
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H01L

## Abstract

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

## Claims

### Claim 1

A multi-chip package comprising:
a semiconductor integrated-circuit (IC) chip comprising:
a plurality of non-volatile memory cells; and
a programmable logic circuit configured to be programmed to perform a logic function, comprising a plurality of input points for an input data set for the logic operation, a multiplexer configured to select, in accordance with the input data set, a resulting value from a plurality of resulting values of a look-up table (LUT) as an output data for the logic operation, and an output point for the output data for the logic operation; and
a memory chip coupling to the semiconductor integrated-circuit (IC) chip, wherein communication between the semiconductor integrated-circuit (IC) chip and the memory chip has a data bit width greater than or equal to 64.

### Claim 2 (depends on 1)

The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a resistive-random-access-memory (RRAM) cell configured to store data associated with one of the plurality of resulting values.

### Claim 3 (depends on 1)

The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a magnetoresistive-random-access-memory (MRAM) cell configured to store data associated with one of the plurality of resulting values.

### Claim 4 (depends on 1)

The multi-chip package of claim 1, wherein the programmable logic circuit comprises a plurality of static-random-access-memory (SRAM) cells configured to store the plurality of resulting values associated with data stored in the plurality of non-volatile memory cells.

### Claim 5 (depends on 4)

The multi-chip package of claim 4, wherein the semiconductor integrated-circuit (IC) chip further comprises a sense amplifier configured to sense and amplify information associated with the data stored in one of the non-volatile memory cells as output data of the sense amplifier, wherein the output data of the sense amplifier is configured to be associated with one of the plurality of resulting values stored in one of the plurality of static-random-access-memory (SRAM) cells.

### Claim 6 (depends on 4)

The multi-chip package of claim 4, wherein each of the plurality of non-volatile memory cells comprises a magnetoresistive-random-access-memory (MRAM) cell.

### Claim 7 (depends on 1)

The multi-chip package of claim 1, wherein the semiconductor integrated-circuit (IC) chip further comprises a transistor configured to form a channel coupling to one of the plurality of non-volatile memory cells based on a voltage level at a gate terminal of the transistor.

### Claim 8 (depends on 1)

The multi-chip package of claim 1, wherein the memory chip comprises a dynamic random-access memory (DRAM) chip.

### Claim 9 (depends on 1)

The multi-chip package of claim 1 further comprising:
an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer, and a polymer layer between the first and second interconnection metal layers, wherein the first interconnection metal layer is connected to the second interconnection metal layer through multiple openings in the polymer layer;
a plurality of first copper bumps between the semiconductor integrated-circuit (IC) chip and the interconnection scheme, wherein each of the plurality of first copper bumps connects the semiconductor integrated-circuit (IC) chip to the first and second interconnection metal layers; and
a plurality of second copper bumps between the memory chip and the interconnection scheme, wherein each of the plurality of second copper bumps connects the memory chip to the first and second interconnection metal layers, wherein the memory chip couples to the semiconductor integrated-circuit (IC) chip through, in sequence, one of the plurality of second copper bumps, the second interconnection metal layer and one of the plurality of first copper bumps, wherein the semiconductor integrated-circuit (IC) chip is in a same plane as the memory chip.

### Claim 10 (depends on 1)

The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a first electrode, a resistive layer on the first electrode, and a second electrode on the resistive layer, wherein the resistive layer is between the first and second electrodes.

### Claim 11 (depends on 10)

The multi-chip package of claim 10, wherein each of the plurality of non-volatile memory cells is configured to be programmed in one of a high resistance state and a low resistance state, wherein the low resistance state has a resistance lower than that of the high resistance state.

### Claim 12 (depends on 10)

The multi-chip package of claim 10, wherein the resistive layer comprises hafnium oxide.

### Claim 13 (depends on 10)

The multi-chip package of claim 10, wherein the resistive layer has a thickness between 1 and 20 nanometers.

### Claim 14 (depends on 1)

The multi-chip package of claim 1, wherein each of the plurality of non-volatile memory cells comprises a first magnetic layer, an oxide layer on the first magnetic layer and a second magnetic layer on the oxide layer, wherein the oxide layer is between the first and second magnetic layers.

### Claim 15 (depends on 14)

The multi-chip package of claim 14, wherein the oxide layer comprises magnesium oxide.

### Claim 16 (depends on 14)

The multi-chip package of claim 14, wherein each of the plurality of non-volatile memory cells further comprises an antiferromagnetic layer under the first magnetic layer, wherein the first magnetic layer is between the antiferromagnetic layer and the oxide layer.

### Claim 17 (depends on 1)

The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises a plurality of I/O ports and at least one I/O-port selection pad configured to select a port from the plurality of I/O ports to output data from the semiconductor integrated-circuit (IC) chip to the data bus in a first clock cycle.

### Claim 18 (depends on 17)

The multi-chip package of claim 17 further comprising a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip coupling to the data bus, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises an I/O port to receive the data, output by the port of the semiconductor integrated-circuit (IC) chip, from the data bus in the first clock cycle.

### Claim 19 (depends on 17)

The multi-chip package of claim 17, wherein the at least one I/O-port selection pad is configured to select the port from the plurality of I/O ports to receive data from the data bus in a second clock cycle.

### Claim 20 (depends on 19)

The multi-chip package of claim 19, wherein the data received by the port of the semiconductor integrated-circuit (IC) chip is output from the memory chip in the second clock cycle.

### Claim 21 (depends on 1)

The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises a plurality of I/O ports and at least one I/O-port selection pad configured to select a port from the plurality of I/O ports to receive data from the data bus to the semiconductor integrated-circuit (IC) chip.

### Claim 22 (depends on 1)

The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises an I/O port configured to receive data from the data bus to the semiconductor integrated-circuit (IC) chip, wherein the I/O port has a plurality of I/O circuits each having an input capacitance between 0.05 and 2 pF.

### Claim 23 (depends on 1)

The multi-chip package of claim 1 further comprising a data bus coupling the semiconductor integrated-circuit (IC) chip to the memory chip, wherein the semiconductor integrated-circuit (IC) chip further comprises an I/O port configured to output data from the semiconductor integrated-circuit (IC) chip to the data bus, wherein the I/O port has a plurality of I/O circuits each having an output capacitance between 0.15 and 2 pF.

### Claim 24 (depends on 1)

The multi-chip package of claim 1, wherein the data bit width is greater than or equal to 256.