# US 10,483,978 B1 · Memory device processing

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- Number: US 10,483,978 B1
- Document ID: US10483978B1
- Status: Granted
- Kind: B1
- Application number: 16/161,825
- Filed: 2018-10-16
- Granted: 2019-11-19
- Earliest claimed: 2018-10-16
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Timothy P Finkbeiner; Troy D. Larsen
- Web page: https://patentgrep.com/patent/US10483978B1

## CPC

- H03K 19/1776: for memories
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier
- G11C 2207/2245: Memory devices with an internal cache buffer
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.

## Claims

### Claim 1

An apparatus, comprising:
a memory device comprising a plurality of banks of memory cells, wherein particular banks of memory cells among the plurality of banks includes a bank processor configured to control memory operations for the bank on which the bank processor is located; and
a system processor resident on a bank of the memory device that does not include the bank processor, wherein the system processor is configured to control performance of memory operations for the memory device.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the system processor is configured to cause performance of the memory operations without transferring a command to circuitry external to the memory device.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the system processor comprises a reduced instruction set computing (RISC-V) processor having increased processing power in comparison to the bank processors on the particular banks.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein each bank among the plurality of banks includes a plurality of extended row address (XRA) components configured to operate as caches for the processor of each bank.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the plurality of memory banks comprises a volatile memory device, and wherein the volatile memory device further includes an input/output interface to couple the volatile memory device to a non-volatile memory device.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the memory device is DRAM device resident on a dual inline memory module (DIMM).

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the system processor is further configured to cause a processing-in-memory operation to be performed by at least one bank of the memory device.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein each bank among the plurality of banks includes:
a first extended row address (XRA) component configured to operate as at least one of an instruction cache for the system processor corresponding to the bank on which the system processor is deployed and as a data cache for the system processor corresponding to the bank on which the system processor is deployed;
a second XRA component configured to operate as a bank-to-bank transfer cache; and
a third XRA component configured to operate as a high-speed interface to store host instructions for the bank.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the banks of memory cells further comprise sensing circuitry configured to perform logical operations on operands stored therein.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the sensing circuitry is further configured to perform logical operations without sending or receiving a command from circuitry external to the memory device.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the plurality of banks that includes the bank processor further include respective very long instruction word (VLIW) machines, and wherein the bank of the memory device that does not include the bank processor does not include a VLIW machine.

### Claim 12

A method, comprising:
receiving, by a system processor resident on a particular memory bank on a memory device, instructions to orchestrate tasks performed by bank processors resident on banks of the memory device that are devoid of the system processor; and
executing, by the system processor, the instructions to orchestrate tasks performed by the bank processors.

### Claim 13 (depends on 12)

The method of claim 12, further comprising executing the instructions to perform the memory operation without sending or receiving commands from circuitry external to the memory device.

### Claim 14 (depends on 12)

The method of claim 12, wherein executing the instructions to orchestrate tasks performed by the bank processors further comprises executing the instructions to cause performance of a processing-in-memory operation using a memory bank that is devoid of the system processor.

### Claim 15 (depends on 12)

The method of claim 12, further comprising receiving, by the system processor, the instructions without enabling a double data rate interface of the memory device.

### Claim 16 (depends on 12)

The method of claim 12, wherein the memory device is DRAM device resident on a dual inline memory module (DIMM).