# US 10,483,976 B1 · Circuits to interpret pin inputs

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- Number: US 10,483,976 B1
- Document ID: US10483976B1
- Status: Granted
- Kind: B1
- Application number: 15/989,135
- Filed: 2018-05-24
- Published: 2019-11-28
- Granted: 2019-11-19
- Earliest claimed: 2018-05-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Jikai Chen; Yanli Fan
- Web page: https://patentgrep.com/patent/US10483976B1

## CPC

- H03K 19/018521: {of complementary type, e.g. CMOS}
- H03K 3/356113: {using additional transistors in the input circuit}
- H03K 3/356165: {using additional transistors in the feedback circuit}
- H03K 5/08: by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

In examples, an apparatus comprises a pin, an input buffer coupled to the pin at an output of the input buffer, a voltage divider circuit coupled to the input buffer at an input of the input buffer, a first current mirror coupled to the input buffer, and a second current mirror coupled to the input buffer. The apparatus also comprises a first output buffer coupled between the input buffer and the first current mirror, and a second output buffer coupled between the input buffer and the second current mirror.

## Claims

### Claim 1

An apparatus comprising:
a pin;
an input buffer coupled to the pin;
a first current mirror coupled to the input buffer, the first current mirror comprising three transistors, each of the three transistors in the first current mirror coupling to a different one of three legs of the apparatus;
a second current mirror coupled to the input buffer, the second current mirror comprising three transistors, each of the three transistors in the second current mirror coupling to a different one of the three legs of the apparatus;
multiple level shifters positioned in a common leg of the three legs;
a voltage divider circuit coupled to the multiple level shifters;
a first output buffer coupled to the input buffer and the first current mirror; and
a second output buffer coupled to the input buffer and the second current mirror.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the input buffer comprises a p-type metal oxide semiconductor field effect transistor (MOSFET) coupled to an n-type MOSFET.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the p-type MOSFET and the n-type MOSFET of the input buffer are positioned in a single leg of the three legs.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the multiple level shifters include first and second metal oxide semiconductor field effect transistors (MOSFETs), wherein the first MOSFET is an n-type MOSFET and the second MOSFET is a p-type MOSFET.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the voltage divider circuit comprises a pair of resistors, and wherein a node between the resistors comprises a node between the first and second MOSFETs of the multiple level shifters.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein at least one of the three transistors in the first current mirror is sized differently than the remaining transistors in the first current mirror, and wherein at least one of the three transistors in the second current mirror is sized differently than the remaining transistors in the second current mirror.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein transistors in the input buffer have width-by-length sizes that are smaller than width-by-length sizes of other transistors coupled to the transistors in the input buffer.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein gates of transistors in the input buffer couple to gates of transistors in the multiple level shifters.

### Claim 9

An apparatus comprising:
a pin;
a first n-type metal oxide semiconductor field effect transistor (MOSFET) coupled to the pin;
a first p-type MOSFET coupled to the pin;
a second p-type MOSFET coupled to the first n-type MOSFET;
a second n-type MOSFET coupled to the first p-type MOSFET;
a third p-type MOSFET coupled to the second p-type MOSFET;
a third n-type MOSFET coupled to the third p-type MOSFET and to the first n-type MOSFET;
a fourth p-type MOSFET coupled to the third n-type MOSFET and to the first p-type MOSFET;
a fourth n-type MOSFET coupled to the fourth p-type MOSFET and to the second n-type MOSFET;
a fifth p-type MOSFET coupled to the second and third p-type MOSFETs;
a fifth n-type MOSFET coupled to the second and fourth n-type MOSFETs;
a voltage divider circuit comprising two resistors, a node between the resistors comprising a node between the third n-type MOSFET and the fourth p-type MOSFET;
a first output buffer coupled to the first n-type MOSFET and the second p-type MOSFET;
a second output buffer coupled to the first p-type MOSFET and the second n-type MOSFET; and
a voltage source coupled to the second, third, and fifth p-type MOSFETs, wherein the second, fourth, and fifth n-type MOSFETs couple to ground.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the first n-type and p-type MOSFETs are sized to carry less current than the second p-type MOSFET.

### Claim 11

An apparatus, comprising:
a voltage source;
a current mirror coupled to the voltage source;
a voltage divider circuit coupled to the voltage source;
multiple level shifters coupled to the voltage divider circuit; and
two or more legs coupled to the current mirror and the multiple level shifters, each of the two or more legs comprising:
a pin;
a first n-type field effect transistor (FET) coupled to the pin;
a first p-type FET coupled to the pin;
a first output buffer coupled to the first n-type FET;
a second output buffer coupled to the first p-type FET;
a second p-type FET coupled to the first output buffer; and
a second n-type FET coupled to the second output buffer.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the first n-type FET has a smaller width-by-length size than the second p-type FET.