# US 10,483,973 B2 · Temperature instability-aware circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,973 B2 - Document ID: US10483973B2 - Status: Granted - Kind: B2 - Application number: 16/156,507 - Filed: 2018-10-10 - Published: 2019-06-06 - Granted: 2019-11-19 - Earliest claimed: 2017-12-06 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Chia-Hui Chen; Wan-Yen Lin; Tsung-Hsin Yu - Web page: https://patentgrep.com/patent/US10483973B2 ## CPC - H03K 19/00384: {in field effect transistor circuits} - H03K 3/356113: {using additional transistors in the input circuit} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A circuit includes: a first type of swing reduction circuit coupled between an input/output pad and a buffer circuit; and a second type of swing reduction circuit coupled between the input/output pad and the buffer circuit, wherein the first type of swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second type of swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage. ## Claims ### Claim 1 A circuit, comprising: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, wherein the first swing reduction circuit comprises a first p-type metal-oxide-semiconductor field-effect-transistor gated by a first bias voltage and comprises a second p-type metal-oxide-semiconductor field-effect-transistor drained by the first bias voltage; and a second swing reduction circuit coupled between the input/output pad and the buffer circuit, wherein the first swing reduction circuit is configured to increase a voltage received by respective gates of a first subset of transistors of the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage, and the second swing reduction circuit is configured to reduce a voltage received by respective gates of a second subset of transistors of the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the second supply voltage is higher than the first supply voltage. ### Claim 3 (depends on 1) The circuit of claim 1, wherein the first supply voltage is a ground voltage (VSS) and the second supply voltage is a power supply voltage (VDD). ### Claim 4 (depends on 1) The circuit of claim 1, wherein the first subset of transistors of the buffer circuit are each a p-type metal-oxide-semiconductor field-effect-transistor, and the second subset of transistors of the buffer circuit are each an n-type metal-oxide-semiconductor field-effect-transistor. ### Claim 5 (depends on 1) The circuit of claim 1, wherein a source of the first p-type metal-oxide-semiconductor field-effect-transistor is coupled to the input/output pad, and a drain of the first p-type metal-oxide-semiconductor field-effect-transistor is coupled to the respective gates of the first subset of transistors of the buffer circuit. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the first bias voltage is higher than the first supply voltage but lower than the second supply voltage. ### Claim 7 (depends on 6) The circuit of claim 6, wherein a source of the first p-type metal-oxide-semiconductor field-effect-transistor and a gate of the second p-type metal-oxide-semiconductor field-effect-transistor are both coupled to the input/output pad, and a drain of the first p-type metal-oxide-semiconductor field-effect-transistor and a source of the second p-type metal-oxide-semiconductor field-effect-transistor are both coupled to the respective gates of the first subset of transistors of the buffer circuit. ### Claim 8 (depends on 1) The circuit of claim 1, wherein the second swing reduction circuit comprises an n-type metal-oxide-semiconductor field-effect-transistor, a gate of the n-type metal-oxide-semiconductor field-effect-transistor being coupled to the second supply voltage, a drain of the n-type metal-oxide-semiconductor field-effect-transistor being coupled to the input/output pad, and a source of the n-type metal-oxide-semiconductor field-effect-transistor being coupled to the respective gates of the second subset of transistors of the buffer circuit. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the second swing reduction circuit comprises a first n-type metal-oxide-semiconductor field-effect-transistor gated by a second bias voltage, and a second n-type metal-oxide-semiconductor field-effect-transistor sourced by the second bias voltage, the second bias voltage being higher than the first supply voltage but lower than the second supply voltage. ### Claim 10 (depends on 9) The circuit of claim 9, wherein a drain of the first n-type metal-oxide-semiconductor field-effect-transistor and a gate of the second n-type metal-oxide-semiconductor field-effect-transistor are both coupled to the input/output pad, and a source of the first n-type metal-oxide-semiconductor field-effect-transistor and a drain of the second n-type metal-oxide-semiconductor field-effect-transistor are both coupled to the respective gates of the second subset of transistors of the buffer circuit. ### Claim 11 A circuit, comprising: a swing reduction circuit coupled between an input/output pad and a buffer circuit, wherein the swing reduction circuit is configured to either increase an input voltage in response to the input voltage being equal to a first supply voltage and provide the increased input voltage to the buffer circuit, or decrease the input voltage in response to the input voltage being equal to a second supply voltage and provide the decreased input voltage to the buffer circuit, and wherein the swing reduction circuit comprises: a first metal-oxide-semiconductor field-effect-transistor gated by a first bias voltage; and a second metal-oxide-semiconductor field-effect-transistor drained by the first bias voltage. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the first and second metal-oxide-semiconductor field-effect-transistors comprise a p-type metal-oxide-semiconductor field-effect-transistor configured to increase the input voltage in response to the input voltage being equal to the first supply voltage and provide the increased input voltage to the buffer circuit. ### Claim 13 (depends on 12) The circuit of claim 12, wherein the p-type metal-oxide-semiconductor field-effect-transistor comprise: a source coupled to the input/output pad, and a drain coupled to respective gates of at least one p-type metal-oxide-semiconductor field-effect-transistor of the buffer circuit. ### Claim 14 (depends on 11) The circuit of claim 11, wherein the first and second metal-oxide-semiconductor field-effect-transistors comprise an n-type metal-oxide-semiconductor field-effect-transistor configured to decrease the input voltage in response to the input voltage being equal to the second supply voltage and provide the decreased input voltage to the buffer circuit. ### Claim 15 (depends on 14) The circuit of claim 14, wherein the n-type metal-oxide-semiconductor field-effect-transistor comprises: a drain coupled to the input/output pad, and a source coupled to respective gates of at least one n-type metal-oxide-semiconductor field-effect-transistor of the buffer circuit. ### Claim 16 (depends on 11) The circuit of claim 11, wherein the first bias voltage is higher than the first supply voltage but lower than the second supply voltage. ### Claim 17 (depends on 11) The circuit of claim 11, wherein the first and second metal-oxide-semiconductor field-effect-transistors are n-type metal-oxide-semiconductor field-effect-transistors. ### Claim 18 A method, comprising: receiving an input voltage ranging from a first supply voltage to a second supply voltage; and either increasing a first voltage received by at least one p-type metal-oxide-semiconductor field-effect-transistor of a buffer circuit in response to the input voltage being equal to the first supply voltage, or decreasing a second voltage received by at least one n-type metal-oxide-semiconductor field-effect-transistor of the buffer circuit in response to the input voltage being equal to the second supply voltage, wherein the first voltage is increased to a first bias voltage applied to a gate of a first transistor that is coupled between the input voltage and the buffer circuit, wherein the second voltage is decreased to a second bias voltage applied to a gate of a second transistor that is coupled between the input voltage and the buffer circuit. ### Claim 19 (depends on 18) The method of claim 18, wherein the first supply voltage is a ground voltage (VSS) and the second supply voltage is a power supply voltage (VDD). ### Claim 20 (depends on 18) The method of claim 18, wherein the first voltage is received by a gate of the at least one p-type metal-oxide-semiconductor field-effect-transistor of the buffer circuit and the second voltage is received by a gate of the at least one n-type metal-oxide-semiconductor field-effect-transistor of the buffer circuit.