# US 10,483,971 B1 · Physical unclonable device and method of maximizing existing process variation for a physically unclonable device

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- Number: US 10,483,971 B1
- Document ID: US10483971B1
- Status: Granted
- Kind: B1
- Application number: 15/980,767
- Filed: 2018-05-16
- Published: 2019-11-21
- Granted: 2019-11-19
- Earliest claimed: 2018-05-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Lien Linus Lu; Cormac Michael O'Connell; Kun-Hsi Li
- Web page: https://patentgrep.com/patent/US10483971B1

## CPC

- H03K 19/00315: {in field-effect transistor circuits}
- G06F 30/33: Design verification, e.g. functional simulation or model checking
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 11/419: Read-write [R-W] circuits
- H10B 10/12: {comprising a MOSFET load element}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 42/405: {using active circuits}
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A physically unclonable function (PUF) device and a method for maximizing existing process variation for a physically unclonable device are provided. The method of maximizing process variation of the PUF device includes: modeling a physically unclonable function (PUF) device, comprising a plurality of PUF cells, selecting the size of transistors in the PUF device to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells, varying the material of the PUF device, and driving the PUF device with a predetermined voltage. The physically unclonable device includes: a plurality of PUF cells, configured to generate an output. Each of the plurality of PUF cells includes a harvester circuit, configured to generate a bit line and a complementary bit line. The harvester circuit is selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells; and a sense amplifier having a plurality of transistors configured to receive a first input signal and a second input signal from the harvester circuit.

## Claims

### Claim 1

A physically unclonable function (PUF) device comprising:
a plurality of PUF cells, configured to generate an output, wherein each of the plurality of PUF cells comprising:
a harvester circuit comprising a first circuit which comprises a first pair of transistors and a second circuit which comprises a second pair of transistors, the harvester circuit is configured to generate a bit line and a complementary bit line, wherein the harvester circuit is selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells,
a sense amplifier comprising a plurality of transistors configured to receive a first input signal and a second input signal from the harvester circuit; and
a pulse evaluation circuit, programmable to generate a pulse evaluation signal coupled to a control terminal of the second pair of transistors.

### Claim 2 (depends on 1)

The PUF device of claim 1, wherein
the first circuit further configured to generate the complementary bit line for a first predetermined time, and
the second circuit further configured to generate the bit line for a second predetermined time.

### Claim 3 (depends on 2)

The PUF device of claim 2, further comprising:
a control terminal of the first pair of transistors are coupled to a pre-charge signal, and
the control terminal of the second pair of transistors are coupled to the pulse evaluation signal with a predetermined delay.

### Claim 4 (depends on 2)

The PUF device of claim 2, wherein the first pair of transistors and the second pair of transistors are IO devices which generate maximum variations in the harvester circuit.

### Claim 5 (depends on 4)

The PUF device of claim 4, wherein the IO devices use a predetermined voltage to power the PUF cells.

### Claim 6 (depends on 1)

The PUF device of claim 1, wherein after the pulse evaluation signal is stopped, the sense amplifier is enabled to translate difference between the bit line and the complementary bit line.

### Claim 7 (depends on 1)

The PUF device of claim 1, wherein the sense amplifier further comprising a third pair of transistors and a fourth pair of transistors, a control terminal of the third pair of transistors receives a bit signal and an output node of the third pair of transistors receives a complementary bit signal from the harvester circuit, and a control terminal of the fourth pair of transistors receives the complementary bit signal and an output node of the fourth pair of transistors receives the bit signal from the harvester circuit.

### Claim 8 (depends on 7)

The PUF device of claim 7, wherein the sense amplifier further comprising:
a bias transistor, coupled to the third pair of transistors and the fourth pair of transistors, to receive an enable signal to turn on the sense amplifier.

### Claim 9 (depends on 7)

The PUF device of claim 7, wherein after evaluating difference between the bit line and the complementary bit line, the sense amplifier generates a latched output result when the bit line and the complementary bit line reaches the stable binary value.

### Claim 10

A physically unclonable function (PUF) device comprising:
a plurality of PUF cells, configured to generate an output, wherein each of the plurality of PUF cells comprising:
an enable/disable complementary metal oxide semiconductor (CMOS) differential logic circuit (ECDL), comprising a first transistor, a second transistor, and a sense amplifier, wherein the sense amplifier comprising a first pair, a second pair and a bias transistor,
the first pair forms an inverter circuit comprising a third transistor and a fourth transistor, and the second pair forms an inverter circuit comprising a fifth transistor and a sixth transistor,
the third transistor and the fifth transistor are IO devices, wherein the IO devices use a predetermined voltage to power the PUF cells,
the IO devices are selected to be smaller than a predetermined size defined according to a design rule check (DRC) and generate maximum variations among the plurality of PUF cells; and
a pulse evaluation circuit, programmable to generate a pulse evaluation signal coupled to a control terminal of the second transistor,
wherein after the pulse evaluation signal is stopped, the sense amplifier is enabled to translate difference between a bit line and the complementary bit line.

### Claim 11 (depends on 10)

The PUF device of claim 10, further comprising:
a control terminal of the first pair receives a bit signal and an output node of the first pair receives a complementary bit signal,
a control terminal of the second pair receives the complementary bit signal and an output node of the second pair receives the bit signal, and
after evaluating difference between the bit line and the complementary bit line, the sense amplifier generates a latched output result when the bit line and the complementary bit line reaches the stable binary value.