# US 10,483,968 B2 · Apparatus and method for determining optimum stack number of RF switch

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- Number: US 10,483,968 B2
- Document ID: US10483968B2
- Status: Granted
- Kind: B2
- Application number: 16/242,518
- Filed: 2019-01-08
- Published: 2019-08-29
- Granted: 2019-11-19
- Earliest claimed: 2018-02-28
- Assignees: Samsung Electro-Mechanics Co., Ltd.
- Applicants: Samsung Electro-Mechanics Co., Ltd.
- Inventors: Byeong Hak Jo; Jeong Hoon Kim; Hyun Paek
- Web page: https://patentgrep.com/patent/US10483968B2

## CPC

- H03K 17/102: {in field-effect transistor switches}
- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- H03K 17/08122: {in field-effect transistor switches}
- H03K 17/08142: {in field-effect transistor switches}
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 2217/0018: Special modifications or use of the back gate voltage of a FET
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An apparatus for determining an optimum stacking number of an RF switch, in which a gate-off voltage and a body-off voltage are used to control transistors stacked in series to enter an OFF state. The apparatus includes a memory configured to store a peak voltage of a high-frequency signal in a corresponding band, and a gate limiting voltage, a drain-source limiting voltage, and a body limiting voltage in a corresponding process for each of the transistors, and a processor configured to calculate a gate terminal voltage, a drain-source voltage, and a body terminal voltage using the peak voltage, the gate limiting voltage, the drain-source limiting voltage, and the body limiting voltage and to determine an optimum stacking number based on the gate terminal voltage, the gate limiting voltage, the drain-source voltage, the drain-source limiting voltage, the body terminal voltage, and the body limiting voltage.

## Claims

### Claim 1

An apparatus for determining an optimum stacking number of a radio frequency (RF) switch, in which a gate-off voltage and a body-off voltage are used to control transistors stacked in series to enter an OFF state, the apparatus comprising:
a memory configured to store a peak voltage of a high-frequency signal in a corresponding band, and to store a gate limiting voltage, a drain-source limiting voltage, and a body limiting voltage in a corresponding process for each of the transistors; and
a processor configured to calculate a gate terminal voltage, a drain-source voltage, and a body terminal voltage using the peak voltage, the gate limiting voltage, the drain-source limiting voltage, and the body limiting voltage stored in the memory and to determine an optimum stacking number based on the gate terminal voltage, the gate limiting voltage, the drain-source voltage, the drain-source limiting voltage, the body terminal voltage, and the body limiting voltage.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the processor comprises:
an input unit configured to receive the peak voltage of the high-frequency signal, the gate limiting voltage, the drain-source limiting voltage, and the body limiting voltage from the memory;
a voltage calculation unit configured to calculate the gate terminal voltage, the drain-source voltage, and the body terminal voltage using the peak voltage, the gate limiting voltage, the drain-source limiting voltage, and the body limiting voltage;
a stacking number calculation unit configured to calculate a stacking number, satisfying a gate stacking number condition in which the gate terminal voltage is lower than the gate limiting voltage, to calculate a stacking number, satisfying a both end stacking number condition in which the drain-source voltage is lower than the drain-source limiting voltage, and to calculate a stacking number satisfying a body stacking number condition in which the body terminal voltage is lower than the body limiting voltage; and
an optimum stacking number determination unit configured to determine the optimum stacking number based on a minimum stacking number among stacking numbers commonly satisfying the gate stacking number condition, the both end stacking number condition, and the body stacking number condition.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the optimum stacking number determination unit is configured to determine the gate-off voltage and the body-off voltage corresponding to the optimum stacking number.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the optimum stacking number determination unit is configured to determine the gate-off voltage and the body-off voltage satisfying a first condition, included in a predetermined negative voltage range, and a second condition, in which the body-off voltage is lower than the gate-off voltage, during determination of the gate-off voltage and the body-off voltage.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the gate terminal voltage includes a gate-drain voltage Vgd and a gate-source voltage Vgs,
the body terminal voltage comprises a body-drain voltage Vbd and a body-source voltage Vbs,
the gate limiting voltage comprises a gate-drain breakdown voltage BVGD and a gate-source threshold voltage Vth,
the drain-source limiting voltage is a drain-source breakdown voltage BVDSS, and
the body limiting voltage comprises a body-drain breakdown voltage BVbd and a body-source diode turn-on voltage Vdi.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the stacking number calculation unit is configured to calculate a first stacking number N1, satisfying Equation 1, and a second stacking number N2, satisfying Equation 2, during calculation of the stacking number satisfying the gate stacking number condition, where
BVGD>Vgd,BVGD>Vpk/2*(N1)−Vg, Equation 1:
Vgs<Vth,Vpk/2*(N2)+Vg<Vth, and Equation 2:
Vpk is a peak voltage and Vg is the gate-off voltage.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the stacking number calculation unit is configured to calculate a third stacking number N3, satisfying Equation 3, during calculation of the stacking number satisfying the both end stacking number condition, where
Vds<BVDSS,(N3)>Vpk/(a*Vg+b), and Equation 3:
a is a negative constant and b is a positive constant.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the stacking number calculation unit is configured to calculate a fourth stacking number N4, satisfying Equation 4, and a fifth stacking number N5, satisfying Equation 5, during calculation of the stacking number satisfying the body stacking number condition, where
BVbd>Vbd,BVbd>Vpk/2*(N4)−Vb, Equation 4:
Vbs<Vdi,Vpk/2*(N5)+Vb<Vdi, and Equation 5:
Vb is the body-off voltage.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the drain-source breakdown voltage BVDSS satisfies Equation 6, where
BVDSS=(a*Vg+b). Equation 6:

### Claim 10

A method for determining an optimum stacking number of a radio frequency (RF) switch, in which a gate-off voltage and a body-off voltage are used to control transistors stacked in series to enter an OFF state, the method comprising:
receiving a peak voltage of a high-frequency signal in a corresponding band, and a gate limiting voltage, a drain-source limiting voltage, and a body limiting voltage in a corresponding process for each of the transistors;
calculating a gate terminal voltage, a drain-source voltage, and a body terminal voltage of each of the transistors;
calculating a stacking number satisfying a gate stacking number condition in which the gate terminal voltage is lower than the gate limiting voltage;
calculating a stacking number satisfying a both end stacking number condition in which the drain-source voltage is lower than the drain-source limiting voltage;
calculating a stacking number satisfying a body stacking number condition in which the body terminal voltage is lower than the body limiting voltage; and
determining the optimum stacking number based on a minimum stacking number among stacking numbers commonly satisfying the gate stacking number condition, the both end stacking number condition, and the body stacking number condition.

### Claim 11 (depends on 10)

The method of claim 10, further comprising determining the gate-off voltage and the body-off voltage corresponding to the optimum stacking number.

### Claim 12 (depends on 11)

The method of claim 11, further comprising determining the gate-off voltage and the body-off voltage satisfying a first condition, included in a predetermined negative voltage range, and a second condition, in which the body-off voltage is lower than the gate-off voltage, during determination of the gate-off voltage and the body-off voltage.

### Claim 13 (depends on 12)

The method of claim 12, wherein the gate terminal voltage includes a gate-drain voltage Vgd and a gate-source voltage Vgs,
the body terminal voltage includes a body-drain voltage Vbd and a body-source voltage Vbs,
the gate limiting voltage includes a gate-drain breakdown voltage BVGD and a gate-source threshold voltage Vth,
the drain-source limiting voltage is a drain-source breakdown voltage BVDSS, and
the body limiting voltage includes a body-drain breakdown voltage BVbd and a body-source diode turn-on voltage Vdi.

### Claim 14 (depends on 13)

The method of claim 13, further comprising calculating a first stacking number N1, satisfying Equation 1, and a second stacking number N2, satisfying Equation 2, during calculation of the stacking number satisfying the gate stacking number condition, where
BVGD>Vgd,BVGD>Vpk/2*(N1)−Vg, Equation 1:
Vgs<Vth,Vpk/2*(N2)+Vg<Vth, and Equation 2:
Vpk is a peak voltage and Vg is the gate-off voltage.

### Claim 15 (depends on 14)

The method of claim 14, further comprising calculating a third stacking number N3, satisfying Equation 3, during calculation of the stacking number satisfying the both end stacking number condition, where
Vds<BVDSS,(N3)>Vpk/(a*Vg+b), and Equation 3:
a is a negative constant and b is a positive constant.

### Claim 16 (depends on 15)

The method of claim 15, wherein the calculating a stacking number satisfying the body stacking number condition calculates a fourth stacking number N4, satisfying Equation 4, and a fifth stacking number N5, satisfying Equation 5, during calculation of the stacking number satisfying the body stacking number condition, where
BVbd>Vbd,BVbd>Vpk/2*(N4)−Vb, Equation 4:
Vbs<Vdi,Vpk/2*(N5)+Vb<Vdi, and Equation 5:
Vb is the body-off voltage.

### Claim 17 (depends on 16)

The method of claim 16, wherein the drain-source breakdown voltage BVDSS satisfies Equation 6, where
BVDSS=(a*Vg+b). Equation 6:

### Claim 18

An apparatus comprising:
a memory configured to store a peak voltage of a high-frequency signal and limiting voltages associated with transistors;
a processor configured to calculate terminal voltages based on the limiting voltages stored in the memory and to determine an optimum stacking number of the transistors based on the limiting voltages and the terminal voltages; and
a voltage generator configured to generate a gate-off voltage and a body-off voltage corresponding to the optimum stacking number determined by the processor.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the transistors are stacked in series in a radio frequency switch and the gate-off voltage and the body-off voltage are used to control the transistors to enter an OFF state.