# US 10,483,960 B2 · Radio frequency switch with low oxide stress > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,960 B2 - Document ID: US10483960B2 - Status: Granted - Kind: B2 - Application number: 16/154,304 - Filed: 2018-10-08 - Published: 2019-02-14 - Granted: 2019-11-19 - Earliest claimed: 2014-07-25 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Qiang Li - Web page: https://patentgrep.com/patent/US10483960B2 ## CPC - H03K 17/04106: {in field-effect transistor switches (H03K17/0412, H03K17/0416 take precedence)} - H03K 17/687: the devices being field-effect transistors - H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A RF switch circuit includes a voltage divider circuit and a semiconductor device. The semiconductor device has an activated state and a deactivated state. The voltage divider circuit has an input terminal connected to a first line and an output terminal connected to a second line. The first line is connected to a power source. A gate terminal of the semiconductor device is connected to the second line. In the activated state, a source terminal and a drain terminal of the semiconductor device are each selectively connected to ground. In the deactivated state, the source terminal and the drain terminal of the semiconductor device are each selectively connected to the power source. ## Claims ### Claim 1 A circuit arrangement comprising a radio frequency (RF) switch circuit, the radio frequency switch circuit comprising: a voltage divider circuit having an input terminal connected to a first line and an output terminal connected to a second line, the first line being connected to a power source for a supply voltage; a semiconductor device having an activated state and a deactivated state, a gate terminal of the semiconductor device being connected to the second line of the voltage divider circuit in the activated state, a source terminal and a drain terminal of the semiconductor device each being selectively connected to ground and in the deactivated state, the source terminal and the drain terminal of the semiconductor device each being selectively connected to the power source, oxide direct current stress between the gate terminal and either or both the source terminal and the drain terminal being maintained below power handling limits of the semiconductor device in the deactivated state and the activated state based upon a direct current gate voltage reduced from the supply voltage by the voltage divider. ### Claim 2 (depends on 1) The circuit arrangement of claim 1, wherein the semiconductor device is a triple-well n-channel metal oxide semiconductor transistor. ### Claim 3 (depends on 1) The circuit arrangement of claim 1, wherein the source terminal of the semiconductor device is connected to radio frequency signal input line. ### Claim 4 (depends on 1) The circuit arrangement of claim 1, wherein the drain terminal of the semiconductor device is connected to a radio frequency signal output line. ### Claim 5 (depends on 1) The circuit assembly of claim 1 further comprising a resistive element connected to the semiconductor device and the output terminal of the voltage divider. ### Claim 6 (depends on 5) The circuit assembly of claim 5 wherein the resistive element is connected to the gate terminal of the semiconductor device. ### Claim 7 (depends on 1) The circuit assembly of claim 1 further comprising a first direct current blocking capacitor connected between the drain terminal of the semiconductor device and a radio frequency signal input. ### Claim 8 (depends on 1) The circuit assembly of claim 1 further comprising a second direct current blocking capacitor connected between the source terminal of the semiconductor device and a radio frequency signal output. ### Claim 9 (depends on 1) The circuit assembly of claim 1 wherein the deactivated state sets a radio frequency power handling limit based on parasitic diode clipping at a predefined level of induced radio frequency voltage. ### Claim 10 (depends on 1) The circuit assembly of claim 1 wherein the voltage divider reduces the supply voltage by half for output to the semiconductor device. ### Claim 11 (depends on 10) The circuit assembly of claim 10 wherein the supply voltage is 5 volts, and the direct current gate voltage is 2.5 volts. ### Claim 12 (depends on 11) The circuit assembly of claim 11 wherein the semiconductor device is a 3.3-volt device. ### Claim 13 (depends on 1) The circuit assembly of claim 1 wherein the voltage divider is a two-resistor voltage divider. ### Claim 14 A method for configuring and operating a semiconductor switch for processing of radio frequency signals, comprising: applying an input voltage over a first line to a voltage divider circuit; applying an output voltage of the voltage divider over a second line to a gate terminal of a triple-well n-channel metal oxide semiconductor transistor, the output voltage of the voltage divider circuit always being above a threshold of the triple-well n-channel metal oxide semiconductor transistor to guarantee switch function, while oxide direct current stress between the gate terminal and either or both the source terminal and the drain terminal being maintained below power handling limits of the triple-well n-channel metal oxide semiconductor transistor in the deactivated state and the activated state based upon a direct current gate voltage reduced from the input voltage by the voltage divider circuit. ### Claim 15 (depends on 14) The method of claim 14 wherein when the triple-well n-channel metal oxide semiconductor transistor is in a deactivated state, a source terminal and a drain terminal of the triple-well NMOS transistor are each selectively connected to a power source, the power source being connected to the voltage divider circuit over the first line. ### Claim 16 (depends on 14) The method of claim 14 wherein when the triple-well n-channel metal oxide semiconductor transistor is in an activated state, a source terminal and a drain terminal of the triple-well n-channel metal oxide semiconductor transistor are each selectively connected to ground. ### Claim 17 (depends on 14) The method of claim 14 wherein the output voltage of the voltage divider is applied over the second line through a resistive element to the gate of the triple-well n-channel metal oxide semiconductor transistor. ### Claim 18 (depends on 14) The method of claim 14 wherein the deactivated state sets a radio frequency power handling limit based on parasitic diode clipping at a predefined level of induced radio frequency voltage. ### Claim 19 A circuit assembly including a radio frequency switch circuit, the assembly comprising: a gate resistor; a voltage divider with an input connected to a power source generating a supply voltage and an output connected to the gate resistor; and a triple-well n-channel metal oxide semiconductor transistor with an activated state and a deactivated state, and including a gate, a source and a drain the gate being connected to the gate resistor and the source and the drain each being selectively connectable to ground to transition the triple-well n-channel metal oxide semiconductor transistor to the activated state and to the power source to transition the triple-well n-channel metal oxide semiconductor transistor to the deactivated state, oxide direct current stress between the gate and either or both the source and the drain being maintained below power handling limits of the triple-well n-channel metal oxide semiconductor transistor in the deactivated state and the activated state based upon a direct current gate voltage reduced from the supply voltage. ### Claim 20 (depends on 19) The circuit assembly of claim 19 wherein the voltage divider reduces the supply voltage by half for output to the semiconductor device.