# US 10,483,957 B2 · Semiconductor device

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- Number: US 10,483,957 B2
- Document ID: US10483957B2
- Status: Granted
- Kind: B2
- Application number: 15/702,341
- Filed: 2017-09-12
- Published: 2018-03-22
- Granted: 2019-11-19
- Earliest claimed: 2016-09-16
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Kazuto Kanomata
- Web page: https://patentgrep.com/patent/US10483957B2

## CPC

- H03K 5/22: Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00)
- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125)
- H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)}
- H04L 25/03885: {adaptive}
- H03K 2005/00019: {Variable delay}
- H03K 2005/00286: {Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency}
- H04L 2025/0349: {as a feedback filter}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.

## Claims

### Claim 1

A semiconductor device comprising:
an addition circuit of adding input data and feedback data and outputting addition data;
a first sampling circuit of sampling the addition data from the addition circuit synchronously with a first clock signal and outputting sampling data;
a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data;
a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and
a phase adjustment circuit, when reference data for adjusting a timing of sampling of the first sampling circuit is output as the addition data from the addition circuit, of adjusting phase of the first clock signal so that sampling data output from the first sampling circuit corresponds to the reference data.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a plurality of delay circuits coupled in series and each operating synchronously with the first clock signal,
wherein an output of the first sampling circuit is supplied to the delay circuit in a first stage in the plurality of delay circuits coupled in series, and
wherein the phase adjustment circuit adjusts phase of the first clock signal on the basis of an output of the first sampling circuit and an output of the plurality of delay circuits.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising a buffer circuit to which the input data is supplied and which supplies the supplied input data to the addition circuit,
wherein at the time of adjusting a delay time, supply of the input data from the buffer circuit to the addition circuit is stopped, and the feedback data is set as the reference data for adjusting the sampling timing.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a temperature sensor of detecting temperature,
wherein the phase adjustment circuit adjusts the phase of the first clock signal on the basis of temperature data from the temperature sensor.

### Claim 5

A semiconductor device comprising:
an addition circuit of adding input data and feedback data and outputting addition data;
a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data;
a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data;
a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit;
a temperature sensor of detecting temperature; and
a phase adjustment circuit of changing a timing of sampling of the first sampling circuit on the basis of temperature data from the temperature sensor.