# US 10,483,955 B2 · Feedback system and method of operating the same

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- Number: US 10,483,955 B2
- Document ID: US10483955B2
- Status: Granted
- Kind: B2
- Application number: 16/030,013
- Filed: 2018-07-09
- Published: 2019-05-23
- Granted: 2019-11-19
- Earliest claimed: 2017-11-20
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Hyun Kim; Soon Ku Kang; Bo Ram Kim
- Web page: https://patentgrep.com/patent/US10483955B2

## CPC

- H03K 5/1534: Transition or edge detectors
- H03K 5/13: Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K 19/0005: {Modifications of input or output impedance}
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

The feedback system includes an input signal generation circuit configured to output an input signal having a level corresponding to a code signal inputted thereto and a lock signal generation circuit configured to output the code signal for controlling a level of the input signal using two reference signals, to generate count data acquired by counting time from when the level of the input signal reaches between levels of the two reference signals to when the level of the input signal becomes higher or lower than the level of any one of the two reference signals, and to output a lock signal for fixing the level of the input signal after time corresponding to a rounded value of a quotient of the count data divided by 2.

## Claims

### Claim 1

A lock signal generation circuit, comprising:
an input signal control circuit configured to receive an input signal and two reference signals and output state signals and a code signal for controlling a level of the input signal, the state signals representing a result of comparison of the input signal with the two reference signals, wherein the state signals include an up/down signal and an ambiguous signal;
a pre-lock signal generator configured to receive the up/down signal, and to output a pre-lock signal to determine a time at which the level of the input signal is to be fixed in response to the up/down signal, wherein the up/down signal represents whether the input signal has a higher or lower level than the two reference signals; and
a signal-processing circuit configured to receive the pre-lock signal and the ambiguous signal, and to output a lock signal to fix the level of the input signal using the ambiguous signal and the pre-lock signal, wherein the ambiguous signal is outputted when the level of the input signal is in between levels of the two reference signals.

### Claim 2 (depends on 1)

The lock signal generation circuit according to claim 1, wherein:
the two reference signals include a first reference signal and a second reference signal, and
the first reference signal has a higher level than the second reference signal.

### Claim 3 (depends on 2)

The lock signal generation circuit according to claim 2, wherein the input signal control unit comprises:
a comparator configured to receive the input signal, the first reference signal, and the second reference signal, to output the up/down signal having a low state when the level of the input signal is lower than a level of the second reference signal, to output the up/down signal having a high state when the level of the input signal is higher than a level of the first reference signal, and to output the ambiguous signal when the level of the input signal is higher than the level of the second reference signal and lower than the level of the first reference signal; and
a code signal generator configured to output an up-code signal for increasing the level of the input signal by 1 code as the code signal when the up/down signal has a low state, and to output a down-code signal for decreasing the level of the input signal by 1 code as the code signal when the up/down signal has a high state.

### Claim 4 (depends on 3)

The lock signal generation circuit according to claim 3, wherein the comparator does not change a state of the up/down signal when the ambiguous signal is outputted.

### Claim 5 (depends on 4)

The lock signal generation circuit according to claim 4, wherein the pre-lock signal generation unit comprises:
an edge detector configured to output an edge detection signal by detecting that the state of the up/down signal changes;
an edge counter configured to count the edge detection signal and to output an edge count signal when a preset number of edge detection signals are inputted; and
a pre-lock signal output circuit configured to output the pre-lock signal using the edge count signal.

### Claim 6 (depends on 5)

The lock signal generation circuit according to claim 5, wherein the signal-processing circuit is configured to:
count a number of codes by which the level of the input signal increases or decreases from when the ambiguous signal is outputted to when the state of the up/down signal changes, and
output the lock signal after the level of the input signal decreases or increases by a number of codes corresponding to a rounded value of a quotient of the counted number of codes divided by 2.

### Claim 7 (depends on 6)

The lock signal generation circuit according to claim 6, wherein the signal-processing circuit comprises:
a first counter configured to count a number of times the ambiguous signal is inputted from when the ambiguous signal is outputted to when the state of the up/down signal changes;
a register configured to store count data indicative of the number of times the ambiguous signal is inputted, which is counted by the first counter;
a second counter configured to receive the pre-lock signal and to output rollback data acquired by delaying the pre-lock signal for a quotient of the count data divided by 2; and
a lock signal output circuit configured to output the lock signal by comparing the rollback data with dead-zone upper bit data, which is the count data from which a least significant bit thereof is excluded.

### Claim 8 (depends on 7)

The lock signal generation circuit according to claim 7, wherein the edge counter is configured to output the edge count signal when the edge detection signal is inputted twice.

### Claim 9 (depends on 8)

The lock signal generation circuit according to claim 8, wherein the pre-lock signal output circuit comprises:
a pre-lock logic circuit configured to output a second pre-lock signal in response to the edge count signal;
a delay configured to output a first pre-lock signal acquired by delaying the second pre-lock signal for a time period during which a level corresponding to the 1 code is changed; and
a multiplexer configured to receive the first pre-lock signal and the second pre-lock signal and to output any one of the first pre-lock signal and the second pre-lock signal as the pre-lock signal depending on dead-zone lower bit data, which is the least significant bit of the count data.

### Claim 10 (depends on 9)

The lock signal generation circuit according to claim 9, wherein the multiplexer is configured to output the second pre-lock signal as the pre-lock signal when the dead-zone lower bit data is equal to 0, and to output the first pre-lock signal as the pre-lock signal when the dead-zone lower bit data is equal to 1.

### Claim 11

A feedback system, comprising:
an input signal generation circuit configured to output an input signal having a level corresponding to a code signal inputted thereto; and
a lock signal generation circuit configured to output the code signal for controlling a level of the input signal using two reference signals, to generate count data acquired by counting a number of clock signals from when the level of the input signal reaches between levels of the two reference signals to when the level of the input signal becomes higher or lower than any one of the two reference signals, and to output a lock signal as a control signal to fix the level of the input signal after a time period elapses, wherein the time period corresponds to a rounded value of a quotient of the count data divided by 2.

### Claim 12 (depends on 11)

The feedback system according to claim 11, wherein the lock signal generation circuit comprises:
an input signal control circuit configured to output the code signal and state signals indicative of a result of comparison of the input signal with the two reference signals, wherein the state signals include an up/down signal and an ambiguous signal;
a pre-lock signal generator configured to receive the up/down signal, and to output a pre-lock signal to determine a time at which the level of the input signal is to be fixed in response to the up/down signal, wherein the up/down signal represents whether the input signal has a higher or lower level than the two reference signals; and
a signal-processing circuit configured to receive the pre-lock signal and the ambiguous signal and to output the lock signal through which control is performed so as to fix the level of the input signal using the ambiguous signal and the pre-lock signal, wherein the ambiguous signal is outputted when the level of the input signal is in between the levels of the two reference signals.

### Claim 13 (depends on 12)

The feedback system according to claim 12, wherein:
the two reference signals include a first reference signal and a second reference signal,
the first reference signal has a higher level than the second reference signal, and
the input signal control circuit comprises:
a comparator configured to receive the input signal, the first reference signal, and the second reference signal, to output the up/down signal having a low state when the level of the input signal is lower than a level of the second reference signal, to output the up/down signal having a high state when the level of the input signal is higher than a level of the first reference signal, and to output the ambiguous signal when the level of the input signal is higher than the level of the second reference signal and lower than the level of the first reference signal; and
a code signal generator configured to output an up-code signal for increasing the level of the input signal by 1 code as the code signal when the up/down signal has a low state, and to output a down-code signal for decreasing the level of the input signal by 1 code as the code signal when the up/down signal has a high state.

### Claim 14 (depends on 13)

The feedback system according to claim 13, wherein the comparator does not change a state of the up/down signal when the ambiguous signal is outputted.

### Claim 15 (depends on 14)

The feedback system according to claim 14, wherein the pre-lock signal generation unit comprises:
an edge detector configured to output an edge detection signal by detecting that the state of the up/down signal changes;
an edge counter configured to count the edge detection signal and to output an edge count signal when a preset number of edge detection signals are inputted; and
a pre-lock signal output circuit configured to output the pre-lock signal using the edge count signal.

### Claim 16 (depends on 15)

The feedback system according to claim 15, wherein the signal-processing circuit is configured to:
count a number of codes by which the level of the input signal increases or decreases from when the ambiguous signal is outputted to when the state of the up/down signal changes, and
output the lock signal after the level of the input signal decreases or increases by a number of codes corresponding to a rounded value of a quotient of the counted number of codes divided by 2.

### Claim 17 (depends on 16)

The feedback system according to claim 16, wherein the signal-processing circuit comprises:
a first counter configured to count a number of times the ambiguous signal is inputted from when the ambiguous signal is outputted to when the state of the up/down signal changes;
a register configured to store count data indicative of the number of times the ambiguous signal is inputted, which is counted by the first counter;
a second counter configured to receive the pre-lock signal and to output rollback data acquired by delaying the pre-lock signal for a quotient of the count data divided by 2; and
a lock signal output circuit configured to output the lock signal by comparing the rollback data with dead-zone upper bit data, which is the count data from which a least significant bit thereof is excluded.

### Claim 18 (depends on 17)

The feedback system according to claim 17, wherein the edge counter is configured to output the edge count signal when the edge detection signal is inputted twice.

### Claim 19 (depends on 18)

The feedback system according to claim 18, wherein the pre-lock signal output circuit comprises:
a pre-lock logic unit configured to output a second pre-lock signal in response to the edge count signal;
a delay unit configured to output a first pre-lock signal acquired by delaying the second pre-lock signal for a time period during which a level corresponding to the 1 code is changed; and
a multiplexer configured to receive the first pre-lock signal and the second pre-lock signal and to output any one of the first pre-lock signal and the second pre-lock signal as the pre-lock signal depending on dead-zone lower bit data, which is the least significant bit of the count data.

### Claim 20 (depends on 19)

The feedback system according to claim 19, wherein the multiplexer is configured to output the second pre-lock signal as the pre-lock signal when the dead-zone lower bit data is equal to 0, and to output the first pre-lock signal as the pre-lock signal when the dead-zone lower bit data is equal to 1.