# US 10,483,949 B2 · Driving circuit for power switch

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- Number: US 10,483,949 B2
- Document ID: US10483949B2
- Status: Granted
- Kind: B2
- Application number: 15/332,623
- Filed: 2016-10-24
- Published: 2017-06-01
- Granted: 2019-11-19
- Earliest claimed: 2015-12-01
- Assignees: Delta Electronics, Inc.
- Applicants: Delta Electronics, Inc.
- Inventors: Pei-Qing Hu; Jian-Hong Zeng; Hao-Yi Ye
- Web page: https://patentgrep.com/patent/US10483949B2

## CPC

- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H03K 17/04123: {in field-effect transistor switches}
- H03K 17/163: {Soft switching}
- H03K 17/687: the devices being field-effect transistors
- H02M 1/346: {Passive non-dissipative snubbers}
- H02M 3/158: including plural semiconductor devices as final control devices for a single load
- H02M 3/1582: {Buck-boost converters (H02M3/1584 takes precedence)}
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

A driving circuit for driving a power switch. The driving circuit and the power switch are collaboratively defined as an equivalent circuit. The equivalent circuit includes a first equivalent capacitor corresponding to an input capacitor of the power switch, an equivalent inductor, and a second equivalent capacitor corresponding to a parasitic parameter of at least one driving switch. In the charging procedure or the discharging of the first equivalent capacitor, a change amount of charges in the first equivalent capacitor while a voltage of the input capacitor is changed from a voltage corresponding to no inductor current to a set voltage is larger than or equal to a change amount of charges in the second equivalent capacitor while the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a steady voltage.

## Claims

### Claim 1

A driving circuit for driving a power switch comprising an input capacitor, the driving circuit comprising:
an inductor;
a resistor comprising a parasitic resistor of the driving circuit; and
a first driving switch and a second driving switch electrically connected with the inductor, wherein the first driving switch and the second driving switch are electrically connected with each other and electrically connected with the inductor, wherein the first driving switch comprises a first parasitic capacitor and the second driving switch comprises a second parasitic capacitor,
wherein the driving circuit is configured such that a first equivalent capacitor is formed corresponding to the input capacitor, and a second equivalent capacitor is formed corresponding to one or both of the first and second parasitic capacitors,
wherein the first equivalent capacitor, the inductor, the resistor and the second equivalent capacitor are serially connected with each other to form an equivalent circuit to charge/discharge the input capacitor of the power switch, and a charging procedure or a discharging procedure of the input capacitor is performed through the equivalent circuit,
wherein during the charging procedure, firstly, the first driving switch and the second driving switch are turned on by turns, which causes a voltage of the input capacitor to increase to a maximum voltage Vp1, and there is substantially no inductor current when the voltage of the input capacitor is at the maximum voltage Vp1, then, the first driving switch and the second driving switch are turned off, which causes the voltage of the input capacitor to decrease from the maximum voltage to a first steady voltage,
wherein during the discharging procedure, firstly, the first driving switch and the second driving switch are turned on by turns, which causes the voltage of the input capacitor to decrease to a minimum voltage Vp2, and there is substantially no inductor current when the voltage of the input capacitor is at the minimum voltage Vp2, then, the first driving switch and the second driving switch are turned off, which causes the voltage of the input capacitor to increase from the minimum voltage Vp2 to a second steady voltage,
wherein the first and second equivalent capacitors are configured such that:
(1) during the charging procedure, while the voltage of the input capacitor is changed from the maximum voltage Vp1 to the first steady voltage, a first amount of charges discharged from the input capacitor is equal to Q1, whereas while the voltage of the input capacitor is changed from the maximum voltage Vp1 to a first set voltage VH, a second amount of charges discharged from the input capacitor is equal to Q2, wherein Q2 is greater than or equal to Q1,
(2) during the discharging procedure, while the voltage of the input capacitor is changed from the minimum voltage Vp2 to the second steady voltage, a third amount of charges discharged from the input capacitor is equal to Q3, whereas while the voltage of the input capacitor is changed from the minimum voltage Vp2 to a second set voltage VL a fourth amount of charges discharged from the input capacitor is equal to Q4, wherein Q4 is greater than or equal to Q3,
(3) the first steady voltage is higher than the first set voltage VH, and the first set voltage VH is higher than a maximum threshold Vmax of a gate terminal of the power switch, and
(4) the second steady voltage is lower than the second set voltage VL, and the second set voltage VL is lower than a minimum threshold Vmin of the gate terminal of the power switch.

### Claim 2 (depends on 1)

The driving circuit according to claim 1, wherein a first terminal of the first driving switch is electrically connected with an input power source, a second terminal of the first driving switch is electrically connected with a first terminal of the second driving switch and a first terminal of the inductor, a second terminal of the second driving switch is connected with a ground terminal, a second terminal of the inductor is electrically connected with a first terminal of the resistor, and a second terminal of the resistor is electrically connected with the input capacitor.

### Claim 3 (depends on 2)

The driving circuit according to claim 2, wherein the first equivalent capacitor is formed corresponding to the input capacitor and the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q1=Coss31×Vo1+Coss32×Vo1
Q2=Ciss×(Vp1−VH)
Q3=(Coss31+Coss32)×(Vcc−Vo2)
Q4=Ciss×(Vp2−VL)
where Coss31 is a capacitance of the first parasitic capacitor, Coss32 is a capacitance of the second parasitic capacitor, Ciss is a capacitance of the input capacitor, Vo1 is the first steady voltage, Vo2 is the second steady voltage and Vcc is a voltage of the input power source.

### Claim 4 (depends on 2)

The driving circuit according to claim 2, wherein the driving circuit further comprises a third driving switch, and the third driving switch has a third parasitic capacitor, wherein a first terminal of the third driving switch is electrically connected with the second terminal of the inductor and the first terminal of the resistor, a second terminal of the third driving switch is electrically connected with the ground terminal, wherein the driving circuit selectively turns on or turns off the first driving switch and the second driving switch to control the charging procedure of the input capacitor, and the driving circuit turns on the third driving switch to control the discharging procedure of the input capacitor.

### Claim 5 (depends on 4)

The driving circuit according to claim 4, wherein the first equivalent capacitor is formed corresponding to the input capacitor and the third parasitic capacitor, the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q1=(Coss31+Coss32)×Vo1
Q2=(Ciss+Coss33)×(Vp1−VH)
where Coss31 is a capacitance of the first parasitic capacitor, Coss32 is a capacitance of the second parasitic capacitor, Ciss is a capacitance of the input capacitor, Vo1 is the first steady voltage, and Coss33 is a capacitance of the third parasitic capacitor.

### Claim 6 (depends on 2)

The driving circuit according to claim 2, wherein the driving circuit further comprises a first clamping circuit and a second clamping circuit, the first clamping circuit comprises a third parasitic capacitor, and the second clamping circuit comprises a fourth parasitic capacitor, wherein a first terminal of the first clamping circuit is connected with the first terminal of the first driving switch and the input power source, a second terminal of the first clamping circuit is connected with the second terminal of the inductor, a first terminal of the second clamping circuit and the first terminal of the resistor, and a second terminal of the second clamping circuit is connected with the ground terminal, wherein when the voltage of the input capacitor is higher than an over-voltage value, the voltage of the input capacitor is clamped to the over-voltage value by the first clamping circuit, wherein when the voltage of the input capacitor is lower than an under-voltage value, the voltage of the input capacitor is clamped to the under-voltage value by the second clamping circuit.

### Claim 7 (depends on 6)

The driving circuit according to claim 6, wherein the first equivalent capacitor is formed corresponding to the input capacitor, the third parasitic capacitor of the first clamping circuit and the fourth parasitic capacitor of the second clamping circuit, the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q1=(Coss31+Coss32)×Vo1
Q2=(Ciss+Coss34+Coss35)×(Vp1−VH)
where Coss31 is a capacitance of the first parasitic capacitor, Coss32 is a capacitance of the second parasitic capacitor, Ciss is a capacitance of the input capacitor, Coss35 is a capacitance of the third parasitic capacitor of the first clamping circuit, Vo1 is the first steady voltage, and Coss34 is a capacitance of the fourth parasitic capacitor of the second clamping circuit.

### Claim 8 (depends on 7)

The driving circuit according to claim 7, wherein:
Q3=(Coss31+Coss32)×(Vcc−Vo2)
Q4=(Ciss+Coss34+Coss35)×(Vp2×VL)
where Vo2 is the second steady voltage, and Vcc is a voltage of the input power source.

### Claim 9 (depends on 2)

The driving circuit according to claim 2, wherein the driving circuit further comprises a first clamping circuit and a third driving switch, the first clamping circuit comprises a third parasitic capacitor, and the third driving switch comprises a fourth parasitic capacitor, wherein a first terminal of the first clamping circuit is connected with the first terminal of the first driving switch and the input power source, a second terminal of the first clamping circuit is connected with the second terminal of the inductor, a first terminal of the third driving switch and the first terminal of the resistor, and a second terminal of the third driving switch is connected with the ground terminal, wherein when the voltage of the input capacitor is higher than an over-voltage value, the voltage of the input capacitor is clamped to the over-voltage value by the first clamping circuit, wherein the driving circuit turns on the third driving switch to control the discharging procedure of the input capacitor.

### Claim 10 (depends on 9)

The driving circuit according to claim 9, wherein the first equivalent capacitor is formed corresponding to the input capacitor, the third parasitic capacitor of the first clamping circuit and the fourth parasitic capacitor of the third driving circuit, the second equivalent capacitor is formed corresponding to the first parasitic capacitor and the second parasitic capacitor, such that:
Q1=(Coss31+Coss32)×Vo1
Q2(Ciss+Coss33+Coss35)×(Vp1−VH)
where Coss31 is a capacitance of the first parasitic capacitor, Coss32 is a capacitance of the second parasitic capacitor, Ciss is a capacitance of the input capacitor, Coss35 is a capacitance of the third parasitic capacitor of the first clamping circuit, Vo1 is the first steady voltage, and Coss33 is a capacitance of the fourth parasitic capacitor.

### Claim 11 (depends on 1)

The driving circuit according to claim 1, wherein a first terminal of the inductor is electrically connected with an input power source, a second terminal of the inductor is electrically connected with a first terminal of the first driving switch and a first terminal of the second driving switch, a second terminal of the second driving switch is electrically connected with a first terminal of the resistor, and a second terminal of the resistor is electrically connected with the input capacitor, and a second terminal of the first driving switch is electrically connected with a ground terminal.

### Claim 12 (depends on 11)

The driving circuit according to claim 11, wherein the first equivalent capacitor is formed corresponding to the input capacitor and the second equivalent capacitor is formed corresponding to the second parasitic capacitor, such that:
Q1=Coss42×(Vo1−Vcc)
Q2=Ciss×(Vp1−VH)
where Coss42 is a capacitance of the second parasitic capacitor of the second driving switch, Ciss is a capacitance of the input capacitor, Vo1 is the first steady voltage, and Vcc is a voltage of the input power source.

### Claim 13 (depends on 12)

The driving circuit according to claim 12, wherein:
Q3=Coss42×(Vp2+Vcc−Vo2)
Q4=Ciss×(Vp2−VL)
where Vo2 is the second steady voltage.

### Claim 14 (depends on 11)

The driving circuit according to claim 11, wherein the driving circuit further comprises a third driving switch and a DC clamping power source, and the third driving switch has a third parasitic capacitor, wherein a first terminal of the third driving switch is electrically connected with the second terminal of the second driving switch and the first terminal of the resistor, and the DC clamping power source is connected between a second terminal of the third driving switch and the ground terminal, wherein when the third driving switch is turned on, the input capacitor is charged by the DC clamping power source, wherein when the third driving switch is turned off, the first driving switch and the second driving switch are selectively turned on or turned off to control the discharging procedure of the input capacitor.

### Claim 15 (depends on 14)

The driving circuit according to claim 14, wherein the first equivalent capacitor is formed corresponding to the input capacitor and the third parasitic capacitor, the second parasitic capacitor is formed corresponding to the second parasitic capacitor of the second driving circuit, such that:
Q1=Coss42×(Vo1−Vcc)
Q2=(Ciss+Coss43)×(Vclamp−VH)
where Coss42 is a capacitance of the second parasitic capacitor of the second driving switch, Ciss is a capacitance of the input capacitor, Coss43 is a capacitance of the third parasitic capacitor, Vo1 is the first steady voltage, Vcc is a voltage of the input power source, Vclamp is equal to the maximum voltage Vp1.

### Claim 16 (depends on 14)

The driving circuit according to claim 14, wherein:
Q3=Coss42×(Vp2+Vcc−Vo2)
Q4=(Ciss+Coss43)×(Vp2−VL)
wherein Coss42 is a capacitance of the second parasitic capacitor of the second driving switch, Ciss is a capacitance of the input capacitor, Coss43 is a capacitance of the third parasitic capacitor, Vo2 is the second steady voltage, and Vcc is a voltage of the input power source.

### Claim 17 (depends on 11)

The driving circuit according to claim 11, wherein the driving circuit further comprises a first clamping circuit and a DC clamping power source, and the first clamping circuit has a third parasitic capacitor, wherein a first terminal of the first clamping circuit is electrically connected with the second terminal of the second driving switch and the first terminal of the resistor, and the DC clamping power source is connected between a second terminal of the first clamping circuit and the ground terminal, wherein when the voltage of the input capacitor is higher than a voltage of the DC clamping power source, the voltage of the input capacitor is clamped to the voltage of the DC clamping power source by the first clamping circuit.

### Claim 18 (depends on 17)

The driving circuit according to claim 17, wherein the first equivalent capacitor is formed corresponding to the input capacitor and the third parasitic capacitor, the second parasitic capacitor is formed corresponding to the second parasitic capacitor of the second driving circuit, such that:
Q1=Coss42×(Vo1−Vcc)
Q2=(Ciss+Coss43)×(Vclamp−VH)
where Coss42 is a capacitance of the second parasitic capacitor of the second driving switch, Ciss is a capacitance of the input capacitor, Coss43 is a capacitance of the third parasitic capacitor, Vo1 is the first steady voltage, Vcc is a voltage of the input power source, and Vclamp is equal to the maximum voltage Vp1.

### Claim 19 (depends on 18)

The driving circuit according to claim 18, wherein:
Q3=Coss42×(Vp2+Vcc−Vo2)
Q4=(Ciss+Coss43)×(Vp2−VL)
where Vo2 is the second steady voltage.

### Claim 20 (depends on 17)

The driving circuit according to claim 17, wherein the driving circuit further comprises a third driving switch, and the third driving switch has a fourth parasitic capacitor, wherein a first terminal of the third driving switch is electrically connected with the first terminal of the first clamping circuit, the second terminal of the second driving switch and the first terminal of the resistor, and a second terminal of the third driving switch is electrically connected with the ground terminal.

### Claim 21 (depends on 20)

The driving circuit according to claim 20, wherein the first equivalent capacitor is formed corresponding to the input capacitor, the third parasitic capacitor and the fourth parasitic capacitor, the second parasitic capacitor is formed corresponding to the second parasitic capacitor of the second driving circuit, such that:
Q1=Coss42×(Vo1−Vcc)
Q2=(Ciss+Coss43+Coss44)×(Vclamp−VH)
where Coss42 is a capacitance of the second parasitic capacitor of the second driving switch, Ciss is a capacitance of the input capacitor, Coss43 is a capacitance of the third parasitic capacitor, Coss44 is a capacitance of the fourth parasitic capacitor, Vo1 is the first steady voltage, Vcc is a voltage of the input power source, and Vclamp is equal to the maximum voltage Vp1.

### Claim 22 (depends on 11)

The driving circuit according to claim 11, wherein the driving circuit further comprises a third driving switch, and the third driving switch has a third parasitic capacitor, wherein a first terminal of the third driving switch is electrically connected with the second terminal of the second driving switch and the first terminal of the resistor, and a second terminal of the third driving switch is electrically connected with the ground terminal, wherein the third driving switch is turned on to control the discharging procedure of the input capacitor.

### Claim 23 (depends on 22)

The driving circuit according to claim 22, wherein the first equivalent capacitor is formed corresponding to the input capacitor and the third parasitic capacitor, the second parasitic capacitor is formed corresponding to the second parasitic capacitor of the second driving circuit, such that:
Q1=Coss42×(Vo1−Vcc)
Q2=(Ciss+Coss43)×(Vclamp−VH)
where Coss42 is a capacitance of the second parasitic capacitor of the second driving switch, Ciss is a capacitance of the input capacitor, Coss43 is a capacitance of the third parasitic capacitor, Vo1 is the first steady voltage, Vcc is a voltage of the input power source, and Vclamp is equal to equal to the maximum voltage Vp1.

### Claim 24 (depends on 22)

The driving circuit according to claim 22, wherein:
Q3=Coss42×(Vp2+Vcc−Vo2)
Q4=(Ciss+Coss43)×(Vp2−VL)
where Vo2 is the second steady voltage.

### Claim 25 (depends on 1)

The driving circuit according to claim 1, further comprising a third driving switch and a fourth driving switch, wherein a first terminal of the first driving switch is electrically connected with an input power source, a second terminal of the first driving switch is electrically connected with a first terminal of the second driving switch and a first terminal of the inductor, a second terminal of the second driving switch is connected with a ground terminal, a first terminal of the fourth driving switch is electrically connected with a first terminal of the resistor, a second terminal of the fourth driving switch is electrically connected with a second terminal of the inductor and a first terminal of the third driving switch, a second terminal of the third driving switch is connected with the ground terminal, and a second terminal of the resistor is electrically connected with the input capacitor.

### Claim 26 (depends on 25)

The driving circuit according to claim 25, wherein the driving circuit selectively turns on or turns off the first driving switch, the second driving switch, third driving switch and the fourth driving switch to control the charging procedure and the discharging procedure of the input capacitor.

### Claim 27 (depends on 26)

The driving circuit according to claim 26, wherein the first equivalent capacitor is formed corresponding to the input capacitor, a third parasitic capacitor of the third driving switch and a fourth parasitic capacitor of the fourth driving switch, the second equivalent capacitor is formed corresponding to the first parasitic capacitor of the first driving switch and the second parasitic capacitor of the second driving switch, such that:
Q1=(Coss51+Coss52)×[VH−(Vp1−Vo1)×(Ciss/Coss54)]
Q2=(Coss53+Coss54)×(Vp1−VH)×(Ciss/Coss54)+Coss53×(Vp1−VH)
where Vo1 is the first steady voltage, Coss51 is a capacitance of the first parasitic capacitor of the first driving switch, Coss52 is a capacitance of the second parasitic capacitor of the second driving switch, Ciss is a capacitance of the input capacitor, Coss53 is a capacitance of the third parasitic capacitor of the third driving switch, and Coss54 is a capacitance of the fourth parasitic capacitor of the fourth driving switch.

### Claim 28 (depends on 27)

The driving circuit according to claim 27, wherein:
Q3=(Coss51+Coss52)×[Vcc−(Vo2−Vp2)×(Ciss/Coss54)]
Q4=(Coss53+Coss54)×(VL−Vp2)×(Ciss/Coss54)+Coss53×(VL−Vp2)
where Vo2 is the second steady voltage.

### Claim 29 (depends on 1)

The driving circuit according to claim 1, wherein a first terminal of the first driving switch is electrically connected with a second terminal of the inductor, a second terminal of the first driving switch is electrically connected with a first terminal of the resistor, a first terminal of the inductor is electrically connected with an input power source, and a second terminal of the resistor is electrically connected with the input capacitor.

### Claim 30 (depends on 29)

The driving circuit according to claim 29, wherein:
Q1=Coss61×(Vo1−Vcc)
Q2=Ciss×(Vp1−VH)
where Vo1 is the first steady voltage, Coss61 is a capacitance of the first parasitic capacitor of the first driving switch, Ciss is a capacitance of the input capacitor, and Vcc is a voltage of the input power source.

### Claim 31 (depends on 30)

The driving circuit according to claim 30, wherein:
Q3=Coss61×(Vcc−Vo2)
Q4=Ciss×(Vp2−VL)
where Vo2 is the second steady voltage.

### Claim 32 (depends on 1)

The driving circuit according to claim 1, wherein the resistor has a resistance causing the first steady voltage and the second steady voltage to be higher than 0.5×(Vp1+Vmax) and lower than 0.5×(Vp2+Vmin) respectively.

### Claim 33 (depends on 1)

The driving circuit according to claim 1, wherein, during the charging procedure, the first driving switch is turned on while the second driving switch is turned off and then the first driving switch is turned off while the second driving switch is turned on to thereby cause the voltage of the input capacitor to increase to the maximum voltage Vp1, whereas during the discharging procedure, the first driving switch is turned off while the second driving switch is turned on and then the first driving switch is turned on while the second driving switch is turned off to thereby cause the voltage of the input capacitor to decrease to the minimum voltage Vp2.