# US 10,483,945 B2 · Switched capacitor based digital step attenuator

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- Number: US 10,483,945 B2
- Document ID: US10483945B2
- Status: Granted
- Kind: B2
- Application number: 15/852,237
- Filed: 2017-12-22
- Published: 2018-06-28
- Granted: 2019-11-19
- Earliest claimed: 2016-12-27
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Rajendrakumar Joish; Visvesvaraya Pentakota
- Web page: https://patentgrep.com/patent/US10483945B2

## CPC

- H03H 11/245: {using field-effect transistor}
- H01F 38/14: Inductive couplings
- H03G 1/0088: {using discontinuously variable devices, e.g. switch-operated}
- H03G 3/001: {Digital control of analog signals}
- H03G 3/3052: {in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver (H03G3/32, H03G3/34 take precedence)}
- H03H 7/25: comprising an element controlled by an electric or magnetic variable (H03H7/27 takes precedence)
- H03K 17/687: the devices being field-effect transistors
- H04B 1/18: Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H)
- H03G 2201/106: being attenuating element
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H03G: CONTROL OF AMPLIFICATION
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04B: TRANSMISSION

## Abstract

The disclosure provides an RF receiver. The RF receiver includes an input driver. The input driver receives a coarse signal, and generates an input signal. A digital step attenuator (DSA) is coupled to the input driver and receives the input signal. An analog to digital converter (ADC) is coupled to the DSA. The DSA includes a serial capacitor coupled to the input driver. The DSA also includes a sampling capacitor coupled to the ADC.

## Claims

### Claim 1

An RF receiver comprising:
an input driver configured to receive a coarse signal, and configured to generate an input signal;
a digital step attenuator (DSA) coupled to the input driver and configured to receive the input signal; and
an analog to digital converter (ADC) coupled to the DSA, wherein the DSA further comprises:
a serial capacitor coupled to the input driver; and
a sampling capacitor coupled to the ADC.

### Claim 2 (depends on 1)

The RF receiver of claim 1, wherein the serial capacitor and the sampling capacitor are configured to attenuate the input signal.

### Claim 3 (depends on 1)

The RF receiver of claim 1, wherein the input driver further comprises:
an antenna configured to receive the coarse signal;
a low noise amplifier (LNA) coupled to the antenna and configured to amplify the coarse signal to generate an amplified signal; and
a filter coupled to the LNA and configured to filter the amplified signal to generate the input signal.

### Claim 4 (depends on 3)

The RF receiver of claim 3, wherein the DSA further comprises:
a secondary resistor coupled between a DSA input terminal and a fixed voltage terminal, the DSA input terminal is coupled to the filter in the input driver; and
a sampling switch coupled between the serial capacitor and a DSA output terminal, wherein the sampling capacitor is coupled to the sampling switch, the DSA output terminal and the fixed voltage terminal, and the serial capacitor is coupled between the DSA input terminal and the sampling switch.

### Claim 5 (depends on 4)

The RF receiver of claim 4, wherein the DSA further comprises a reliability capacitor coupled to the serial capacitor, the sampling switch and the fixed voltage terminal.

### Claim 6 (depends on 4)

The RF receiver of claim 4, wherein the ADC is coupled to the DSA output terminal, and the ADC is configured to generate an output signal at an output terminal.

### Claim 7 (depends on 6)

The RF receiver of claim 6 further comprising an AGC (automatic gain control) block coupled to the output terminal and the DSA, the AGC block configured to receive the output signal as a feedback and configured to generate a program signal, the program signal is provided to the DSA.

### Claim 8

An RF receiver comprising a digital step attenuator (DSA), the DSA comprising:
an array of secondary resistors coupled to a DSA input terminal;
a set of first switches coupled between the array of secondary resistors and a fixed voltage terminal, each first switch of the set of first switches is coupled between a secondary resistor of the array of secondary resistors and the fixed voltage terminal; and
an array of serial capacitors coupled between the DSA input terminal and a set of second switches, wherein each second switch of the set of second switches is coupled between a serial capacitor of the array of serial capacitors and the fixed voltage terminal.

### Claim 9 (depends on 8)

The RF receiver of claim 8, wherein the DSA further comprises:
an array of sampling switches coupled between the array of serial capacitors and a DSA output terminal, each sampling switch of the array of sampling switches is coupled to a serial capacitor of the array of serial capacitors, a second switch of the set of second switches and the DSA output terminal;
a set of third switches coupled to the DSA output terminal; and
an array of sampling capacitors coupled to the set of third switches, each sampling capacitor of the array of sampling capacitors is coupled between a third switch of the set of third switches and the fixed voltage terminal.

### Claim 10 (depends on 8)

The RF receiver of claim 8 further comprising an input driver coupled to the DSA input terminal, the input driver further comprising:
an antenna configured to receive a coarse signal;
a low noise amplifier (LNA) coupled to the antenna and configured to amplify the coarse signal to generate an amplified signal; and
a filter coupled between the LNA and the DSA input terminal and configured to filter the amplified signal to generate an input signal.

### Claim 11 (depends on 8)

The RF receiver of claim 8, wherein the DSA further comprises:
a set of fourth switches coupled between the array of serial capacitors and a second node, each fourth switch of the set of fourth switches is coupled between a serial capacitor of the array of serial capacitors and the second node; and
a set of fifth switches coupled between the second node and an array of reliability capacitors, each fifth switch of the set of fifth switches is coupled between the second node and a reliability capacitor of the array of reliability capacitors, wherein one end of each reliability capacitor is coupled to the fixed voltage terminal.

### Claim 12 (depends on 8)

The RF receiver of claim 8 further comprising:
an analog to digital converter (ADC) coupled to the DSA output terminal and configured to generate an output signal at an output terminal; and
an AGC (automatic gain control) block coupled between the output terminal and the DSA, the AGC block is configured to receive the output signal as a feedback and configured to generate a program signal, the program signal is provided to the DSA.

### Claim 13

A computing device comprising:
a processing unit;
a memory module coupled to the processing unit; and
an RF receiver coupled to the processing unit and the memory module, the RF receiver further comprising:
an input driver configured to receive a coarse signal, and configured to generate an input signal;
a digital step attenuator (DSA) coupled to the input driver and configured to receive the input signal; and
an analog to digital converter (ADC) coupled to the DSA, wherein the DSA further comprises:
a serial capacitor coupled to the input driver; and
a sampling capacitor coupled to the ADC.

### Claim 14 (depends on 13)

The computing device of claim 13, wherein the DSA further comprises:
a secondary resistor coupled between a DSA input terminal and a fixed voltage terminal, the DSA input terminal is coupled to the filter in the input driver; and
a sampling switch coupled to the serial capacitor and a DSA output terminal, wherein the sampling capacitor is coupled to the sampling switch, the DSA output terminal and the fixed voltage terminal and the serial capacitor is coupled between the DSA input terminal and the sampling switch.

### Claim 15 (depends on 14)

The computing device of claim 14, wherein the DSA further comprises a reliability capacitor coupled to the serial capacitor, the sampling switch and the fixed voltage terminal.

### Claim 16

A method comprising:
receiving an attenuation setting from an automatic gain control (AGC) block;
receiving an input signal in a digital step attenuator (DSA), the DSA is coupled to the AGC block;
fixing value of a serial capacitor and a sampling capacitor in the DSA based on the attenuation setting;
closing a sampling switch during a sample phase;
charging the serial capacitor and the sampling capacitor by the input signal, wherein the serial capacitor and the sampling capacitor are in series;
opening the sampling switch during a hold phase; and
providing a charge accumulated on the sampling capacitor to an analog to digital converter (ADC), the ADC coupled between the DSA and the AGC block.

### Claim 17 (depends on 16)

The method of claim 16 further comprising fixing value of a secondary resistor in the DSA based on the attenuation setting.

### Claim 18 (depends on 16)

The method of claim 16 further comprising fixing value of a reliability capacitor in the DSA based on the attenuation setting.

### Claim 19 (depends on 16)

The method of claim 16 further comprising attenuating the input signal by the serial capacitor and the sampling capacitor.

### Claim 20 (depends on 16)

The method of claim 16 further comprising :
generating an output signal by the ADC based on the charge accumulated on the sampling capacitor; and
generating a program signal based on the output signal, the program signal includes the attenuation setting.