# US 10,483,937 B2 · Transceiver circuit and configuration method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,937 B2 - Document ID: US10483937B2 - Status: Granted - Kind: B2 - Application number: 16/144,255 - Filed: 2018-09-27 - Published: 2019-05-30 - Granted: 2019-11-19 - Earliest claimed: 2017-11-27 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corp. - Inventors: Jian-You Chen; Cheng-Wei Luo; Kuan-Yu Shih - Web page: https://patentgrep.com/patent/US10483937B2 ## CPC - H03H 7/0115: {comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence)} - H04B 1/1027: {assessing signal quality or detecting noise/interference for the received signal} - H03H 7/42: Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns - H03H 2001/0085: {Multilayer, e.g. LTCC, HTCC, green sheets} - H03H 2007/013: {Notch or bandstop filters} - H04B 2001/1063: {using a notch filter} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H04B: TRANSMISSION ## Abstract A transceiver circuit including: a substrate; a signal coupler configured on the substrate and including a coiled first conductive layer pattern; and a notch filter configured on the substrate and including a coiled second conductive layer pattern; wherein each of the first conductive layer pattern and the second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis. ## Claims ### Claim 1 A transceiver circuit, comprising: a substrate; a signal coupler configured on the substrate and comprising a coiled first conductive layer pattern; and a notch filter configured on the substrate and comprising a coiled second conductive layer pattern; wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis; wherein the coiled first conductive layer pattern is arranged as a substantially circular pattern and the coiled second conductive layer pattern is arranged as a substantially two-circle pattern; wherein the substantially two-circle pattern comprises two circle patterns disposed apart from and adjacent to each other. ### Claim 2 (depends on 1) The transceiver circuit of claim 1, wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a second virtual axis perpendicular to the first virtual axis. ### Claim 3 (depends on 2) The transceiver circuit of claim 2, wherein the coiled second conductive layer pattern is configured inside the coiled first conductive layer pattern. ### Claim 4 (depends on 3) The transceiver circuit of claim 3, wherein the coiled first conductive layer pattern and the coiled second conductive layer pattern are respectively arranged as a substantially circular pattern with a same geometric center. ### Claim 5 (depends on 3) The transceiver circuit of claim 3, wherein the notch filter comprising a first capacitor and a second capacitor; the coiled first conductive layer pattern comprising a first end and a second end; the coiled second conductive layer pattern comprising a third end and a fourth end; the first capacitor being electrically connected between the first end and the third end; and the second capacitor being electrically connected between the second end and the fourth end. ### Claim 6 (depends on 3) The transceiver circuit of claim 3, wherein the notch filter comprising a first capacitor and a second capacitor; the coiled first conductive layer pattern comprising a first end and a second end; the substantially two-circle pattern providing a first inductor and a second inductor; the first inductor being electrically connected between the first end and the first capacitor; and the second inductor being electrically connected between the second end and the second capacitor. ### Claim 7 A transceiver circuit, comprising: a substrate; a signal coupler configured on the substrate and comprising a coiled first conductive layer pattern; and a notch filter configured on the substrate and comprising a coiled second conductive layer pattern; wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis; wherein the coiled second conductive layer pattern is configured around the coiled first conductive layer pattern. ### Claim 8 (depends on 7) The transceiver circuit of claim 7, wherein the coiled first conductive layer pattern is arranged as a substantially circular pattern as a polygon and the coiled second conductive layer pattern comprises serially connected circular patterns configured respectively outside at least two sides of the polygon. ### Claim 9 A method of transceiver circuit configuration, comprising: configuring a signal coupler on a substrate, the signal coupler comprising a coiled first conductive layer pattern; and configuring a notch filter on the substrate, the notch filter comprising a coiled second conductive layer pattern; wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis; wherein the coiled first conductive layer pattern is arranged as a substantially circular pattern and the coiled second conductive layer pattern is arranged as a substantially two-circle pattern; wherein the substantially two-circle pattern comprises two circle patterns disposed apart from and adjacent to each other. ### Claim 10 (depends on 9) The method of transceiver circuit configuration of claim 9, wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a second virtual axis perpendicular to the first virtual axis. ### Claim 11 (depends on 10) The method of transceiver circuit configuration of claim 10, wherein the coiled second conductive layer pattern is configured inside the coiled first conductive layer pattern. ### Claim 12 (depends on 11) The method of transceiver circuit configuration of claim 11, wherein the coiled first conductive layer pattern and the coiled second conductive layer pattern are respectively arranged as a substantially circular pattern with a same geometric center. ### Claim 13 (depends on 11) The method of transceiver circuit configuration of claim 11, wherein the substrate comprising a multilayer structure and the coiled first conductive layer pattern and the coiled second conductive layer pattern are configured across different layers of the multilayer structure. ### Claim 14 (depends on 11) The method of transceiver circuit configuration of claim 11, wherein the coiled first conductive layer pattern comprising a first end and a second end; the coiled second conductive layer pattern comprising a third end and a fourth end; the method further comprising: electrically connecting a first capacitor between the first end and the third end and electrically connecting a second capacitor between the second end and the fourth end. ### Claim 15 (depends on 11) The method of transceiver circuit configuration of claim 11, wherein the coiled first conductive layer pattern comprising a first end and a second end; the substantially two-circle pattern providing a first inductor and a second inductor; the method further comprising: configuring a first capacitor and a second capacitor such that the first inductor is electrically connected between the first end and the first capacitor and the second inductor is electrically connected between the second end and the second capacitor. ### Claim 16 A method of transceiver circuit configuration: configuring a signal coupler on a substrate, the signal coupler comprising a coiled first conductive layer pattern; and configuring a notch filter on the substrate, the notch filter comprising a coiled second conductive layer pattern; wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis; wherein the coiled second conductive layer pattern is configured around the coiled first conductive layer pattern. ### Claim 17 (depends on 16) The method of transceiver circuit configuration of claim 16, wherein the coiled first conductive layer pattern is arranged as a substantially circular pattern as a polygon and the coiled second conductive layer pattern comprises serially connected circular patterns configured respectively outside at least two sides of the polygon. ### Claim 18 (depends on 16) The method of transceiver circuit configuration of claim 16, wherein the coiled first conductive layer pattern is arranged as a substantially circular pattern as an octagon; the coiled second conductive layer pattern comprising four serially connected circular patterns configured respectively outside two sets of sides of the octagon which are parallel and facing each other.