# US 10,483,936 B2 · Band stop filter structures and methods of forming and operating same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,936 B2 - Document ID: US10483936B2 - Status: Granted - Kind: B2 - Application number: 15/863,184 - Filed: 2018-01-05 - Published: 2019-03-28 - Granted: 2019-11-19 - Earliest claimed: 2017-09-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Ming Hsien Tsai - Web page: https://patentgrep.com/patent/US10483936B2 ## CPC - H03H 7/0115: {comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence)} - H03H 7/09: Filters comprising mutual inductance - H10D 1/20: Inductors - H10D 1/68: Capacitors having no potential barriers - H10W 20/43: Layouts of interconnections - H10W 20/496: {Capacitor integral with wiring layers} - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H01F 2017/0026: {Multilayer LC-filter} - H03H 2001/0078: {comprising spiral inductor on a substrate} - H03H 2001/0085: {Multilayer, e.g. LTCC, HTCC, green sheets} - H03H 2007/013: {Notch or bandstop filters} - H10W 20/427: {Power or ground buses} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES ## Abstract A filter structure including a ground plane wherein the ground plane is in a first metal layer of an integrated circuit (IC) package. The filter structure further includes a plate in a second metal layer of the IC package. The filter structure further includes a dielectric layer between the ground plane and the plate, wherein the ground plane, the dielectric layer, and the plate are thereby configured as a capacitive device. The filter structure further includes an inductive device in a third metal layer of the IC package, wherein the inductive device is electrically connected to the plate. ## Claims ### Claim 1 A filter structure comprising: a ground plane in a first metal layer of an integrated circuit (IC) package; a plate in a second metal layer of the IC package; a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device; and an inductive device in a third metal layer of the IC package, wherein the inductive device is electrically connected to the plate, and the inductive device comprises two symmetrical paths electrically connected at a center of the inductive device. ### Claim 2 (depends on 1) The filter structure of claim 1, wherein the plate is positioned between the ground plane and the inductive device. ### Claim 3 (depends on 1) The filter structure of claim 1, wherein a perimeter of the plate is aligned with a perimeter of the inductive device. ### Claim 4 (depends on 1) The filter structure of claim 1, wherein the two symmetrical paths comprise two symmetrical spiral paths. ### Claim 5 (depends on 4) The filter structure of claim 4, wherein each path of the two symmetrical spiral paths has a width w, the two symmetrical spiral paths are separated by a spacing s, and a ratio s/w has a value ranging from 1 to 2. ### Claim 6 (depends on 1) The filter structure of claim 1, further comprising a via extending from the center of the inductive device to the plate. ### Claim 7 (depends on 1) The filter structure of claim 1, wherein the plate and the inductive device are part of a first unit cell, and the filter structure comprises an array of unit cells including the first unit cell. ### Claim 8 (depends on 7) The filter structure of claim 7, wherein each unit cell of the array of unit cells includes the ground plane. ### Claim 9 (depends on 7) The filter structure of claim 7, wherein the array of unit cells is one of a 1×4 array, a 1×8 array, a 2×3 array, or a 3×3 array. ### Claim 10 (depends on 1) The filter structure of claim 1, wherein the inductive device is part of a power distribution path of the IC package. ### Claim 11 A method of forming a filter structure, the method comprising: forming a ground plane in a first post-passivation interconnect (PPI) layer of an integrated circuit (IC) package; forming a plate in a second PPI layer of the IC package; depositing a dielectric layer between the ground plane and the plate; forming an inductive device in a third PPI layer of the IC package; and constructing an electrical connection between the plate and the inductive device, wherein the forming the ground plane, the forming the plate, and the depositing the dielectric layer are part of constructing a capacitive device, and the forming the plate and the forming the inductive device include forming a perimeter of the plate and a perimeter of the inductive device aligned in a direction perpendicular to a plane of the ground plane. ### Claim 12 (depends on 11) The method of claim 11, wherein the constructing the electrical connection between the plate and the inductive device comprises constructing a via between the second PPI layer and the third PPI layer. ### Claim 13 (depends on 11) The method of claim 11, wherein the forming the inductive device comprises forming a first spiral path and a second spiral path, and the first spiral path and the second spiral path are rotationally symmetrical spiral paths. ### Claim 14 (depends on 11) The method of claim 11, wherein the forming the inductive device comprises forming a spiral path having a width w and a spacing s, and a ratio s/w has a value ranging from 1 to 2. ### Claim 15 (depends on 11) The method of claim 11, wherein the forming the plate is part of forming a plurality of plates, the forming the inductive device is part of forming a plurality of inductive devices, each inductive device of the plurality of inductive devices being electrically connected to a corresponding plate of the plurality of plates, and the constructing the capacitive device is part of constructing a plurality of capacitive devices, each capacitive device of the plurality of capacitive devices including the ground plane and a corresponding plate of the plurality of plates. ### Claim 16 A method of filtering a signal, the method comprising: receiving an input signal at a first terminal of a filter structure in an integrated circuit (IC) package; reducing a high frequency component of the input signal using the filter structure to generate an output signal; and providing the output signal at a second terminal of the filter structure, wherein the filter structure comprises: an inductive device in a first metal layer of the IC package, the inductive device comprising two symmetrical paths electrically connected at a center of the inductive device; and a capacitive device electrically connected to the inductive device, the capacitive device comprising a first plate in a second metal layer of the IC package and a second plate in a third metal layer of the IC package. ### Claim 17 (depends on 16) The method of claim 16, wherein the receiving the input signal at the first terminal of the filter structure comprises receiving the input signal at a first terminal of the inductive device, the providing the output signal at the second terminal of the filter structure comprises providing the output signal at a second terminal of the inductive device, and the capacitive device is electrically connected to the inductive device through a third terminal at the center of the inductive device. ### Claim 18 (depends on 16) The method of claim 16, wherein the filter structure further comprises another inductive device in the first metal layer of the IC package electrically connected to another capacitive device, the another capacitive device comprising the first plate and a third plate in the third metal layer of the IC package, the receiving the input signal at the first terminal of the filter structure comprises receiving the input signal at a terminal of the inductive device, and the providing the output signal at the second terminal of the filter structure comprises providing the output signal at a terminal of the another inductive device. ### Claim 19 (depends on 16) The method of claim 16, wherein the reducing the high frequency component of the input signal comprises reducing the high frequency component based on a predetermined resonance frequency corresponding to a size of the inductive device and a size of the capacitive device. ### Claim 20 (depends on 19) The method of claim 19, wherein the predetermined resonance frequency is greater than 1 gigahertz (GHz).