# US 10,483,702 B2 · High speed communication jack > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,702 B2 - Document ID: US10483702B2 - Status: Granted - Kind: B2 - Application number: 16/192,139 - Filed: 2018-11-15 - Published: 2019-03-21 - Granted: 2019-11-19 - Earliest claimed: 2012-02-13 - Assignees: Sentinel Connector Systems, Inc. - Applicants: Sentinel Connector Systems, Inc. - Inventors: Brett D. Robinson - Web page: https://patentgrep.com/patent/US10483702B2 ## CPC - H01R 24/64: for high frequency, e.g. RJ 45 - H01R 13/646: specially adapted for high-frequency, e.g. structures providing an impedance match or phase match (non-coaxed protective earth or shield arrangements H01R13/648; coaxed connectors specially adapted for high frequency H01R24/40) - H01R 13/6474: by variation of conductive properties, e.g. by dimension variations - H01R 13/6625: {with capacitive component} - H01R 13/7195: with planar filters with openings for contacts - H01R 43/205: {with a panel or printed circuit board} - H05K 1/0218: {by printed shielding conductors, ground planes or power plane (H05K1/0236 takes precedence)} - H05K 1/0228: {Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245)} - H05K 1/09: Use of materials for the {conductive, e.g. } metallic pattern - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/162: {incorporating printed capacitors} - H01R 13/6581: Shield structure - H01R 13/6658: {on printed circuit board (H01R13/6666 - H01R13/6691 take precedence)} - H01R 2107/00: Four or more poles - Y10T 29/49165: by forming conductive walled aperture in base - Y10T 29/49218: with deforming - H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A circuit board for a high speed communication jack including a rigid circuit board in the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a middle layer in the substrate, with each trace extending from a corresponding one of the plurality of vias, a first shielding layer on a first side of the middle layer in the substrate, a second shielding layer on a second side of the middle layer in the substrate, and a third shielding layer adjacent to the second shielding layer. ## Claims ### Claim 1 A high speed communication jack comprising: a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug; a shielding case surrounding the housing; a circuit board disposed in part between the shielding case and the housing, wherein the circuit board comprises a substrate having a first side and a second side opposite the first side, a plurality of pin vias extending through the substrate where each of the pin vias is configured to accommodate a pin on the housing, a plurality of traces on the first side of the substrate where each trace extends from a corresponding one of the plurality of pin vias; a shielding trace layer disposed on the first side of the substrate including a pair of shielding tabs disposed on opposite edges of the first side of the substrate and a shielding trace disposed on the first side of the substrate opposite the first plurality of pin vias where the shielding trace extends between and connects the shielding tabs, a shielding plane on the second side of the substrate, a plurality of return vias extending through the substrate with each of the return vias connecting the shielding trace layer and the shielding plane, wherein, a height, width, length and spacing of at least two traces are adjusted such that an impedance of the at least two traces is substantially the same. ### Claim 2 (depends on 1) The high speed communication jack of claim 1, wherein each trace includes a first portion having a variable width and a second portion having a substantially contact width. ### Claim 3 (depends on 2) The high speed communication jack of claim 2, wherein the first portion is disposed non-coplanar with the second portion. ### Claim 4 (depends on 1) The high speed communication jack of claim 1, wherein the shielding plane engages the shielding case. ### Claim 5 (depends on 1) The high speed communication jack of claim 1, wherein a capacitor is formed by a coating surrounding a periphery of each pin via and the shielding layer. ### Claim 6 (depends on 5) The high speed communication jack of claim 5, wherein a distance between the shielding layer and the traces is adjusted such that the capacitor has a value of between approximately 0.1 pf and approximately 0.5 pf. ### Claim 7 A circuit board for a high speed communication jack having a housing with a shielding case, the circuit board disposed between the housing and the shielding case comprising: a substrate having a first side and a second side opposite the first side, a plurality of pin vias extending through the substrate where each of the pin vias is configured to accommodate a pin on the housing, a plurality of traces on the first side of the substrate where each trace extends from a corresponding one of the plurality of pin vias; a shielding trace layer disposed on the first side of the substrate including a pair of shielding tabs disposed on opposite edges of the first side of the substrate and a shielding trace disposed on the first side of the substrate opposite the first plurality of pin vias where the shielding trace extends between and connects the shielding tabs, a shielding plane on the second side of the substrate, a plurality of return vias extending through the substrate with each of the return vias connecting the shielding trace layer and the shielding plane, wherein, the substrate is non-coplanar and a height, width, length and spacing of at least two traces are adjusted such that an impedance of the at least two traces is substantially the same. ### Claim 8 (depends on 7) The circuit board of claim 7, wherein a capacitor is formed by a coating surrounding a periphery of each pin via and the shielding layer. ### Claim 9 (depends on 8) The circuit board of claim 8, wherein a distance between the shielding layer and the traces is adjusted such that the capacitor has a value of between approximately 0.1 pf and approximately 0.5 pf. ### Claim 10 (depends on 7) The circuit board of claim 7, wherein the substrate comprises a dielectric material having a dielectric constant greater than 3.0.