# US 10,483,653 B2 · Fast memory access control for phase and gain

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- Number: US 10,483,653 B2
- Document ID: US10483653B2
- Status: Granted
- Kind: B2
- Application number: 16/100,408
- Filed: 2018-08-10
- Published: 2019-03-21
- Granted: 2019-11-19
- Earliest claimed: 2017-09-18
- Assignees: Integrated Device Technology, Inc.
- Applicants: Integrated Device Technology, Inc.
- Inventors: Samet Zihir; Tumay Kanar; Naveen Krishna Yanduru
- Web page: https://patentgrep.com/patent/US10483653B2

## CPC

- H01Q 21/0006: {Particular feeding systems}
- H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}
- H01Q 1/48: Earthing means; Earth screens; Counterpoises
- H01Q 1/523: {between antennas of an array}
- H01Q 1/526: {Electromagnetic shields}
- H01Q 3/28: varying the amplitude
- H01Q 3/36: with variable phase-shifters
- H01Q 19/30: the primary active element being centre-fed and substantially straight, e.g. Yagi antenna
- H01Q 21/0025: {Modular arrays}
- H01Q 21/062: {using dipole aerials; (H01Q21/067, H01Q21/068 take precedence)}
- H01Q 21/065: {Patch antenna array}
- H03F 1/0211: {with control of the supply voltage or current}
- H03F 1/0261: {with control of the polarisation voltage or current, e.g. gliding Class A}
- H03F 1/3282: {Acting on the phase and the amplitude of the input signal}
- H03F 1/565: {using inductive elements}
- H03F 3/19: with semiconductor devices only
- H03F 3/195: in integrated circuits
- H03F 3/245: {with semiconductor devices only}
- H03F 3/45089: {Non-folded cascode stages}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 3/68: Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)}
- H03G 3/3042: {in modulators, frequency-changers, transmitters or power amplifiers}
- H03H 7/487: {particularly adapted as coupling circuit between transmitters and antennas}
- H03K 21/10: comprising logic circuits
- H04B 1/0458: {Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages (matching circuits in general H03H)}
- H04B 1/18: Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H)
- H04B 1/401: for selecting or indicating operating mode
- H04B 1/44: Transmit/receive switching
- H04B 1/48: in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)}
- H04B 7/0617: {for beam forming}
- H03F 2200/294: the amplifier being a low noise amplifier [LNA]
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H03F: AMPLIFIERS
- H03G: CONTROL OF AMPLIFICATION
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04B: TRANSMISSION

## Abstract

An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of transceiver circuits while a corresponding one of the control signals is in an active state. The transceiver circuits may be updated with the setting values from the registers within a predetermined time.

## Claims

### Claim 1

An apparatus comprising:
a switching circuit configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal, wherein a single one of said pulses is generated in a single one of said control signals at a time during each of said cycles of said enable signal; and
a plurality of registers hardwired as a plurality of subsets, wherein (i) each of said subsets of said registers is configured to (a) buffer a plurality of setting values received from a memory and (b) present said setting values from said registers to a plurality of transceiver circuits while a corresponding one of said control signals is in an active state, and (ii) said transceiver circuits are updated with said setting values from said registers within a predetermined time.

### Claim 2 (depends on 1)

The apparatus according to claim 1, wherein said predetermined time (i) starts when said corresponding control signal transitions to said active state, continues through transfer of said setting values from said registers to said transceiver circuits and ends when said transceiver circuits update said setting values to steer a radio frequency beam generated by said transceiver circuits and (ii) is no greater than 30 nanoseconds.

### Claim 3 (depends on 1)

The apparatus according to claim 1, further comprising a plurality of additional registers configured to (i) buffer a plurality of bias values and (ii) present said bias values to said transceiver circuits, wherein said bias values trim said transceiver circuits without steering a radio frequency beam generated by said transceiver circuits.

### Claim 4 (depends on 1)

The apparatus according to claim 1, wherein (i) each of said registers has an output port hardwired directly to a corresponding input port of said transceiver circuits and (ii) said output ports of said registers are in a high-impedance state while said corresponding control signal is in an inactive state.

### Claim 5 (depends on 1)

The apparatus according to claim 1, wherein said setting values are moved from a single active one of said subsets of said registers to all of said transceiver circuits in parallel.

### Claim 6 (depends on 1)

The apparatus according to claim 1, wherein a radio frequency beam generated by said transceiver circuits has a frequency in a range of 24 gigahertz to 44 gigahertz.

### Claim 7 (depends on 1)

The apparatus according to claim 1, wherein said switching circuit, said registers and said transceiver circuits are configured to form part of a fifth generation wireless communications system.

### Claim 8 (depends on 1)

The apparatus according to claim 1, wherein said subsets of said setting values correspond to a plurality of patterns of a radio frequency beam generated by said transceiver circuits.

### Claim 9 (depends on 1)

The apparatus according to claim 1, wherein said switching circuit comprises:
a counter configured to generate a count value by counting said cycles of said enable signal;
a decoder configured to generate a plurality of decode signals by decoding said count value, wherein a single one of said decode signals is active at a time; and
a logic circuit configured to generate said control signals by gating said enable signal with said decode signals.

### Claim 10

A method for fast memory access control, comprising the steps of:
buffering a plurality of setting values received from a memory in a plurality of registers hardwired as a plurality of subsets;
generating a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal_, wherein a single one of said pulses is generated in a single one of said control signals at a time during each of said cycles of said enable signal; and
presenting said setting values from a single one of said subsets of said registers to a plurality of transceiver circuits while a corresponding one of said control signals is in an active state, wherein said transceiver circuits are updated with said setting values from said registers within a predetermined time.

### Claim 11 (depends on 10)

The method according to claim 10, wherein said predetermined time (i) starts when said corresponding control signal transitions to said active state, continues through transfer of said setting values from said registers to said transceiver circuits and ends when said transceiver circuits update said setting values to steer a radio frequency beam generated by said transceiver circuits and (ii) is no greater than 30 nanoseconds.

### Claim 12 (depends on 10)

The method according to claim 10, further comprising:
buffering a plurality of bias values in a plurality of additional registers; and
presenting said bias values from said additional registers to said transceiver circuits, wherein said bias values trim said transceiver circuits without steering a radio frequency beam generated by said transceiver circuits.

### Claim 13 (depends on 10)

The method according to claim 10, further comprising the step of:
transferring data from output ports of each of said registers directly to corresponding input ports of said transceiver circuits, wherein said output ports of said registers are in a high-impedance state while said corresponding control signal is in an inactive state.

### Claim 14 (depends on 10)

The method according to claim 10, further comprising the step of:
moving said setting values from a single active one of said subsets of said registers to all of said transceiver circuits in parallel.

### Claim 15 (depends on 10)

The method according to claim 10, wherein a radio frequency beam generated by said transceiver circuits has a frequency in a range of 24 gigahertz to 44 gigahertz.

### Claim 16 (depends on 10)

The method according to claim 10, wherein the steps are implemented in a fifth generation wireless communications system.

### Claim 17 (depends on 10)

The method according to claim 10, wherein said subsets of said setting values correspond to a plurality of patterns of a radio frequency beam generated by said transceiver circuits.

### Claim 18 (depends on 10)

The method according to claim 10, wherein said generation of said control signals comprises the steps of:
generating a count value by counting said cycles of said enable signal;
generating a plurality of decode signals by decoding said count value, wherein a single one of said decode signals is active at a time; and
generating said control signals by gating said enable signal with said decode signals.

### Claim 19

An apparatus comprising:
a switching circuit configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal;
a plurality of first registers hardwired as a plurality of subsets, wherein (i) each of said subsets of said first registers is configured to (a) buffer a plurality of setting values received from a memory and (b) present said setting values from said registers to a plurality of transceiver circuits while a corresponding one of said control signals is in an active state, and (ii) said transceiver circuits are updated with said setting values from said registers within a predetermined time; and
a plurality of second registers configured to (i) buffer a plurality of bias values and (ii) present said bias values to said transceiver circuits, wherein said bias values trim said transceiver circuits without steering a radio frequency beam generated by said transceiver circuits.

### Claim 20 (depends on 19)

The apparatus according to claim 19, wherein said predetermined time (i) starts when said corresponding control signal transitions to said active state, continues through transfer of said setting values from said first registers to said transceiver circuits and ends when said transceiver circuits update said setting values to steer said radio frequency beam generated by said transceiver circuits.