# US 10,483,461 B2 · Embedded MRAM in interconnects and method for producing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,461 B2
- Document ID: US10483461B2
- Status: Granted
- Kind: B2
- Application number: 15/957,506
- Filed: 2018-04-19
- Published: 2019-10-24
- Granted: 2019-11-19
- Earliest claimed: 2018-04-19
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Wanbing Yi; Curtis Chun-I Hsieh; Yi Jiang; Bharat Bhushan; Mahesh Bhatkar; Juan Boon Tan
- Web page: https://patentgrep.com/patent/US10483461B2

## CPC

- H10N 50/01: Manufacture or treatment
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.

## Claims

### Claim 1

A device comprising:
a first interlayer dielectric (ILD) layer including a first metal (Mx) level;
a capping layer formed over the first ILD layer;
magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer;
a second metal (Mx+1) level formed in the second ILD layer;
a second capping layer formed over the second ILD layer;
a third metal (Mx+2) level formed in a third ILD layer over the second capping layer;
oxide spacers formed on sides of metal filled vias, the metal filled vias connecting the Mx level to the MTJ;
copper (Cu) filled vias (Vx) connecting the Mx level to the Mx+1 level; and
Cu filled vias (Vx+1) connecting the Mx+1 level to the Mx+2 level.

### Claim 2 (depends on 1)

The device according to claim 1, wherein:
the MTJ is formed in a memory region of the device,
a hardmask (HM) is formed over the MTJ, and
nitride spacers are formed on sides of the HM and MTJ.

### Claim 3 (depends on 2)

The device according to claim 2,
wherein with the metal filled vias comprise tungsten (W) and tantalum nitride (TaN), or the metal filled vias comprise ruthenium (Ru) or cobalt (Co).

### Claim 4 (depends on 1)

The device according to claim 1, wherein the first and second capping layers comprise silicon carbon nitride (SiCN).

### Claim 5 (depends on 1)

The device according to claim 1, wherein the wherein the HM further comprises an inert metal disposed over the HM, the inert metal comprising ruthenium (Ru), platinum (Pt) or aluminum (Al).

### Claim 6 (depends on 1)

The device according to claim 1, wherein the Mx, Mx+1, and Mx+2 levels comprise Cu.

### Claim 7 (depends on 1)

The device according to claim 1, wherein the first, second and third ILD layers comprise an ultralow-k (ULK) dielectric material.

### Claim 8

A method comprising:
forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level;
forming a capping layer over the first ILD layer;
forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer;
forming a second metal (Mx+1) level in the second ILD layer;
forming a second capping layer over the second ILD layer;
forming a third metal (Mx+2) level in a third ILD layer over the second capping layer;
forming oxide spacers on sides of metal filled vias, the metal filled vias connecting the Mx level to the MTJ;
forming copper (Cu) filled vias (Vx) connecting the Mx level to the Mx+1 level; and
forming Cu filled vias (Vx+1) connecting the Mx+1 level to the Mx+2 level.

### Claim 9 (depends on 8)

The method according to claim 8, further comprising:
forming the MTJ in a memory region of the device;
forming a hardmask (HM) over the MTJ; and
forming nitride spacers on sides of the HM and MTJ.

### Claim 10 (depends on 8)

The method according to claim 8,
wherein with the metal filled vias comprise tungsten (W) and a tantalum nitride (TaN), or the metal filled vias comprise ruthenium (Ru) or cobalt (Co).