# US 10,483,446 B2 · Electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,446 B2 - Document ID: US10483446B2 - Status: Granted - Kind: B2 - Application number: 15/750,316 - Filed: 2015-08-06 - Published: 2018-08-09 - Granted: 2019-11-19 - Earliest claimed: 2015-08-06 - Assignees: OSRAM Opto Semiconductors GmbH - Applicants: OSRAM Opto Semiconductors GmbH - Inventors: Kok Eng Ng; Wui Chai Chew; Choo Kean Lim; Mardiana Khalid - Web page: https://patentgrep.com/patent/US10483446B2 ## CPC - H10H 20/8585: {being an interconnection} - H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls - H10H 20/8581: {characterised by their material} - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/073: {of die-attach connectors} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10H 20/0364: {of interconnections} - H10H 20/851: Wavelength conversion means - H10W 72/075: {of bond wires} - H10W 72/07536: {Soldering or alloying} - H10W 72/07554: {changes in dispositions} - H10W 72/325: {Die-attach connectors having a filler embedded in a matrix} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/354: {comprising polymers} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An electronic device includes a carrier and a semiconductor chip, wherein the carrier includes a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier includes a solder terminal for electrical contacting arranged on the second dielectric layer. ## Claims ### Claim 1 An electronic device comprising a carrier and a semiconductor chip, wherein the carrier comprises a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier comprises a solder terminal for electrical contacting arranged on the second dielectric layer. ### Claim 2 (depends on 1) The electronic device according to claim 1, wherein the second dielectric layer comprises an opening by which the mounting area is provided. ### Claim 3 (depends on 1) The electronic device according to claim 1, wherein the carrier comprises a mounting pad arranged on the first dielectric layer in the mounting area, and the semiconductor chip is arranged on the mounting pad. ### Claim 4 (depends on 1) The electronic device according to claim 1, wherein the carrier comprises a metal base layer on which the first dielectric layer is arranged. ### Claim 5 (depends on 1) The electronic device according to claim 1, wherein the carrier comprises a contact layer arranged on the second dielectric layer and a covering layer partially covering the contact layer, and the solder terminal is provided by a region of the contact layer not covered by the covering layer. ### Claim 6 (depends on 1) The electronic device according to claim 1, wherein the carrier comprises a further solder terminal arranged on the second dielectric layer for electrical contacting. ### Claim 7 (depends on 1) The electronic device according to claim 1, satisfying at least one of: the semiconductor chip is an optoelectronic semiconductor chip, or the electronic device comprises several semiconductor chips arranged on the carrier in the mounting area. ### Claim 8 (depends on 1) A method of producing the electronic device according to claim 1, comprising: providing a first dielectric layer; providing a second dielectric layer, wherein a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer; arranging the second dielectric layer on the first dielectric layer so that a carrier is produced, wherein the carrier comprises a mounting area in which the first dielectric layer is not covered by the second dielectric layer; providing a solder terminal arranged on the second dielectric layer; and arranging a semiconductor chip on the carrier in the mounting area. ### Claim 9 (depends on 8) The method according to claim 8, further comprising forming an opening in the second dielectric layer by which the mounting area of the carrier is provided. ### Claim 10 (depends on 8) The method according to claim 8, wherein the first dielectric layer is provided with a metallic layer arranged on the first dielectric layer, the metallic layer is structured so that a mounting pad arranged on the first dielectric layer is provided, and the semiconductor chip is arranged on the mounting pad. ### Claim 11 (depends on 8) The method according to claim 8, wherein the first dielectric layer is provided with a metal base layer on which the first dielectric layer is arranged. ### Claim 12 (depends on 8) The method according to claim 8, wherein the second dielectric layer is provided with a metallic layer arranged on the second dielectric layer, the metallic layer is structured so that a contact layer arranged on the second dielectric layer is provided, and a covering layer is formed which partially covers the contact layer so that the solder terminal is provided by a region of the contact layer not covered by the covering layer. ### Claim 13 An electronic device comprising a carrier and a semiconductor chip, wherein the carrier comprises a first dielectric layer and a second dielectric layer, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, the carrier comprises a solder terminal for electrical contacting arranged on the second dielectric layer, the carrier comprises a contact layer arranged on the second dielectric layer, the carrier comprises a covering layer directly adjoining the contact layer and partially covering the contact layer, and the solder terminal is provided by a region of the contact layer which is not covered by the covering layer. ### Claim 14 (depends on 13) The electronic device according to claim 13, wherein the covering layer comprises an insulating material. ### Claim 15 (depends on 13) The electronic device according to claim 13, wherein the carrier comprises a contact area, the contact area is provided by a further region of the contact layer not covered by the covering layer, and an electrical connection structure is attached to the contact area and to the semiconductor chip such that the semiconductor chip is electrically connected to the solder terminal. ### Claim 16 An electronic device comprising a carrier and a semiconductor chip, wherein the carrier comprises a first dielectric layer and a second dielectric layer, each of the first and the second dielectric layer is made of a resin-based composite material, a thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer, the second dielectric layer is arranged on the first dielectric layer and partially covers the first dielectric layer, the semiconductor chip is arranged on the carrier in a mounting area in which the first dielectric layer is not covered by the second dielectric layer, and the carrier comprises a solder terminal for electrical contacting arranged on the second dielectric layer. ### Claim 17 (depends on 1) The electronic device according to claim 1, wherein the first dielectric layer comprises a thermal conductivity with a minimum value of 10 W/mK, and the second dielectric layer comprises a thermal conductivity with a maximum value of 5 W/mK. ### Claim 18 (depends on 1) The electronic device according to claim 1, wherein the first dielectric layer comprises a thermal conductivity of 10 W/mK to 20 W/mK, and the second dielectric layer comprises a thermal conductivity below 2 W/mk or below 1 W/mk. ### Claim 19 (depends on 1) The electronic device according to claim 1, wherein the first and the second dielectric layer comprise thermal conductivities selected from the group consisting of: 1.3 W/mK; 2.0 W/mK, 2.2 W/mK, 2.7 W/mK and 3.0 W/mK. ### Claim 20 (depends on 1) The electronic device according to claim 1, wherein the first dielectric layer comprises a thermal conductivity of 3.0 W/mK, and the second dielectric layer comprises a thermal conductivity of 1.3 W/mK.