# US 10,483,398 B2 · Semiconductor device with gate stack

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- Number: US 10,483,398 B2
- Document ID: US10483398B2
- Status: Granted
- Kind: B2
- Application number: 16/042,164
- Filed: 2018-07-23
- Published: 2018-12-13
- Granted: 2019-11-19
- Earliest claimed: 2015-06-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Che-Cheng Chang; Chih-Han Lin
- Web page: https://patentgrep.com/patent/US10483398B2

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/511: {for IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The semiconductor device also includes a protection element over the gate stack, and a top and a bottom of the protection element have different widths. The semiconductor device further includes a spacer over a side surface of the protection element and a sidewall of the gate stack. In addition, the semiconductor device includes a conductive contact electrically connected to a conductive feature over the semiconductor substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate stack over a semiconductor substrate, wherein the gate stack has a work function layer and a metal filling, and tops of the work function layer and the metal filling are at different height levels;
a protection element over the gate stack, wherein a top and a bottom of the protection element have different widths;
a spacer over a side surface of the protection element and a sidewall of the gate stack;
a conductive feature over the semiconductor substrate; and
a conductive contact electrically connected to the conductive feature.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the conductive contact is in direct contact with the protection element.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the conductive contact is separated from the protection element.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the gate stack has a top side and a bottom side, and the top side and the bottom side of the gate stack have different widths.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the spacer has an inner sidewall and an outer sidewall, the inner sidewall is between the outer sidewall and the gate stack, and an upper portion of the inner sidewall inclines towards the outer sidewall.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the conductive feature is a source/drain feature.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the protection element and the spacer are made of different materials.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the conductive contact extends across an interface between the spacer and the protection element.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a first dielectric layer surrounding a lower portion of the conductive contact; and
a second dielectric layer surrounding an upper portion of the conductive contact.

### Claim 10

A semiconductor device, comprising:
a gate stack over a fin structure;
a protection element over the gate stack, wherein a portion of the gate stack extends into the protection element;
a spacer over a side surface of the protection element and a sidewall of the gate stack; and
a conductive contact electrically connected to a source/drain feature over the fin structure.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the spacer and the protection element are made of different materials.

### Claim 12 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising:
a first dielectric layer surrounding a lower portion of the conductive contact; and
a second dielectric layer surrounding an upper portion of the conductive contact.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, wherein the upper portion of the conductive contact is wider than the lower portion of the conductive contact.

### Claim 14 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the conductive contact extends across an interface between the spacer and the protection element.

### Claim 15

A semiconductor device, comprising:
a gate stack over a semiconductor substrate;
a protection element over the gate stack; and
a first spacer and a second spacer located on opposite sides of the gate stack, wherein the first spacer has a first inclined surface, the second spacer has a second inclined surface facing the first inclined surface of the first spacer, and a portion of the gate stack is higher than a bottom of the first inclined surface.

### Claim 16 (depends on 15)

The semiconductor device as claimed in claim 15, wherein a top and a bottom of the gate stack respectively have a first width and a second width, the first width and the second width are measured along directions parallel to each other, and the first width and the second width are different from each other.

### Claim 17 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the first spacer has an outer sidewall, and the first inclined surface is between the outer sidewall of the first spacer and the second inclined surface of the second spacer.

### Claim 18 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the gate stack comprises a work function layer and a metal filling, and tops of the work function layer and the metal filling are at different height levels.

### Claim 19 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the gate stack comprises a work function layer and a metal filling, and tops of the work function layer and the metal filling are substantially coplanar.

### Claim 20 (depends on 15)

The semiconductor device as claimed in claim 15, wherein the gate stack comprises a conductive electrode, and a top surface of the conductive electrode is higher than the bottom of the first inclined surface.