# US 10,483,396 B1 · Interfacial layer between fin and source/drain region

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- Number: US 10,483,396 B1
- Document ID: US10483396B1
- Status: Granted
- Kind: B1
- Application number: 16/004,677
- Filed: 2018-06-11
- Published: 2019-12-12
- Granted: 2019-11-19
- Earliest claimed: 2018-06-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Yun Chin; Chii-Horng Li; Chien-Wei Lee; Hsueh-Chang Sung; Heng-Wen Ting; Roger Tai; Pei-Ren Jeng; Tzu-Hsiang Hsu; Yen-Ru Lee; Yan-Ting Lin; Davie Liu
- Web page: https://patentgrep.com/patent/US10483396B1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

## Claims

### Claim 1

A semiconductor structure comprising:
a substrate;
a fin on the substrate, the fin comprising silicon germanium and having recessed portions;
an interfacial layer over the recessed portions of the fin, the interfacial layer having a thickness in a range from about 1 nm to about 4 nm, wherein the interfacial layer encapsulates impurities on a surface of the fin; and
a source/drain region over the interfacial layer, the source/drain region comprising silicon germanium.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the fin has a germanium atomic percent content in a range from about 5% to about 40%.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the source/drain region comprises a germanium atomic percent content in a range from about 25% to about 70%.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the source/drain region comprise a p-type dopant.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the interfacial layer has a surface roughness in a range from about 2 nm RMS or less RMS.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the interfacial layer comprises silicon germanium.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the interfacial layer has a silicon atomic percent content in a range from about 90% to about 99.9%.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the interfacial layer comprises silicon germanium, the interfacial layer having a higher silicon atomic percent content than the source/drain region and the fin.

### Claim 9

A method of manufacturing a semiconductor device, the method comprising:
forming a fin on a substrate;
forming a gate structure over the fin;
forming a recess in the fin proximate the gate structure;
forming an interfacial layer in the recess, the interfacial layer comprising silicon germanium, wherein the interfacial layer has a silicon atomic percent content of about 90% or more; and
growing an epitaxial source/drain region over the interfacial layer by epitaxial growth.

### Claim 10 (depends on 9)

The method of claim 9, wherein the interfacial layer is formed by providing a silicon precursor.

### Claim 11 (depends on 10)

The method of claim 10, wherein the silicon precursor comprises silane.

### Claim 12 (depends on 10)

The method of claim 10, wherein silane volatilizes impurities from a surface of the fin.

### Claim 13 (depends on 9)

The method of claim 9, wherein the interfacial layer provides a surface roughness less than about 2 nm RMS for the growing of the epitaxial source/drain region.

### Claim 14 (depends on 9)

The method of claim 9, wherein the interfacial layer encapsulates impurities on a surface of the fin.

### Claim 15 (depends on 9)

The method of claim 9, wherein the interfacial layer comprises silicon germanium, the interfacial layer having a higher silicon atomic percent content than the epitaxial source/drain region and the fin.

### Claim 16

A semiconductor structure comprising:
a substrate;
a fin on the substrate, wherein the fin comprises silicon germanium;
a first interfacial layer over a first portion of the fin, wherein the first interfacial layer comprises silicon germanium;
a second interfacial layer over a second portion of the fin, wherein the second interfacial layer comprises silicon germanium, wherein the first interfacial layer and the second interfacial layer have a height variation within 5 nm;
a first source/drain region on the first interfacial layer, wherein the first source/drain region comprises silicon germanium, the silicon germanium of the first interfacial layer having a higher silicon atomic percent content than the silicon germanium of the fin and the silicon germanium of the first source/drain region; and
a second source/drain region on the second interfacial layer, wherein the second source/drain region comprises silicon germanium, the silicon germanium of the second interfacial layer having a higher silicon atomic percent content than the silicon germanium of the fin and the silicon germanium of the second source/drain region.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein the first interfacial layer and the second interfacial layer each have a thickness in a range from about 1 nm to about 4 nm.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein the first interfacial layer and the second interfacial layer each have a silicon atomic percent content in a range from about 90% to about 99.9%.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, wherein the fin has a germanium atomic percent content in a range from about 5% to about 40%.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, wherein the first source/drain region and the second source/drain region have a height variation of less than about 10 nm.