# US 10,483,395 B2 · Method for fabricating semiconductor device

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- Number: US 10,483,395 B2
- Document ID: US10483395B2
- Status: Granted
- Kind: B2
- Application number: 15/849,599
- Filed: 2017-12-20
- Published: 2019-05-23
- Granted: 2019-11-19
- Earliest claimed: 2017-11-23
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chun-Hao Lin; Hsin-Yu Chen; Shou-Wei Hsieh
- Web page: https://patentgrep.com/patent/US10483395B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 84/0123: {Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6506: {Formation of intermediate materials}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 76/20: of masks comprising organic materials
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first buffer layer on the first fin-shaped structure and the second fin-shaped structure; removing the first buffer layer on the first region; and performing a curing process so that a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.

## Claims

### Claim 1

A method for fabricating semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region;
forming a first liner on the first fin-shaped structure and the second fin-shaped structure;
forming a first buffer layer on the first liner;
removing the first buffer layer on the first region;
forming an insulating layer on the first fin-shaped structure and the second fin-shaped structure; and
performing a curing process to combine the first buffer layer and the insulating layer into one unit while the first liner is on the first fin-shaped structure and the second fin-shaped structure and a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming the first buffer layer on the first liner;
forming a patterned mask on the second region; and
using the patterned mask to remove part of the first buffer layer on the first region.

### Claim 3 (depends on 2)

The method of claim 2, further comprising performing an atomic layer deposition (ALD) process to form the first liner.

### Claim 4 (depends on 2)

The method of claim 2, further comprising forming a second liner on sidewalls of the first fin-shaped structure and the second fin-shaped structure before forming the first liner.

### Claim 5 (depends on 4)

The method of claim 4, further comprising performing an in-situ steam generation (ISSG) process to form the second liner.

### Claim 6 (depends on 4)

The method of claim 4, wherein the first liner and the second liner comprise same material.

### Claim 7 (depends on 4)

The method of claim 4, wherein the first liner and the second liner comprise silicon oxide.

### Claim 8 (depends on 2)

The method of claim 2, further comprising:
removing the patterned mask;
forming a second buffer layer on the first region and the second region;
forming an insulating layer on the second buffer layer;
performing the curing process after forming the insulating layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first buffer layer and the second buffer layer comprise same material.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first buffer layer and the second buffer layer comprise amorphous silicon.