# US 10,483,394 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,483,394 B2
- Document ID: US10483394B2
- Status: Granted
- Kind: B2
- Application number: 16/056,148
- Filed: 2018-08-06
- Published: 2018-11-29
- Granted: 2019-11-19
- Earliest claimed: 2015-01-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Cheng-Yen Yu; Che-Cheng Chang; Tung-Wen Cheng; Zhe-Hao Zhang; Bo-Feng Young
- Web page: https://patentgrep.com/patent/US10483394B2

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3408: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D 62/82: Heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a Fin FET device including:
a first fin structure disposed over a substrate;
an isolation insulating layer disposed over the substrate; and
a first source/drain stressor layer made of semiconductor material and disposed over the first fin structure, wherein:
an upper surface of the isolation insulating layer has a valley portion and a peak portion disposed between the valley portion and the first fin structure, and
a height Ha of an interface between the first fin structure and the first source/drain stressor layer measured from the substrate is greater than a height Hb of the valley portion measured from the substrate, and is less than a height Hc of the peak portion measured from the substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a difference between Ha and Hb is in a range from 10 nm to 70 nm.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the Fin FET device further includes:
a second fin structure disposed adjacent to the first fin structure; and
a second source/drain stressor layer disposed over the second fin structure, and
the height Hb is measured at a center position between the first fin structure and the second fin structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the interface has an U-shape.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a depth of the U-shape is 0.5 nm to 100 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first source/drain stressor layer includes at least one of SiP, SiC and SiCP.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first stressor layer includes SiGe.

### Claim 8

A semiconductor device, comprising:
a Fin FET device including:
a first fin structure disposed over a substrate;
an isolation insulating layer disposed over the substrate;
a first source/drain stressor layer made of semiconductor material and disposed over the first fin structure; and
an interlayer dielectric layer, wherein:
an interface between the interlayer dielectric layer and an upper surface of the isolation insulating layer has a valley portion and a peak portion disposed between the valley portion and the first fin structure, and
a height Ha of an interface between the first fin structure and the first source/drain stressor layer measured from the substrate is less than a height Hb of the valley portion measured from the substrate, and is less than a height Hc of the peak portion measured from the substrate.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein a difference between Ha and Hb is in a range from 10 nm to 70 nm.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein:
the Fin FET device further includes:
a second fin structure disposed adjacent to the first fin structure; and
a second source/drain stressor layer disposed over the second fin structure, and
the height Hb is measured at a center position between the first fin structure and the second fin structure.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the interface has an U-shape.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein a depth of the U-shape is 0.5 nm to 100 nm.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the first source/drain stressor layer includes at least one of SiP, SiC and SiCP.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the first stressor layer includes SiGe.

### Claim 15

A semiconductor device, comprising:
an isolation insulating layer disposed over a substrate;
a first fin structure disposed over the substrate;
a second fin structure disposed over the substrate;
a first source/drain stressor layer disposed over the first fin structure and made of a different material than the first fin structure; and
a second source/drain stressor layer disposed over the second fin structure and made of a same material as the first stressor layer,
an upper surface of the isolation insulating layer between the first fin structure and the second fin structure has a U-shape having a valley portion having a minimum height between the first fin structure and the second fin structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a height Ha of an interface between the first fin structure and the first source/drain stressor layer measured from the substrate is greater than a height Hb of a bottom of the U-shape measured from the substrate.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the height Ha is less than a largest height of the isolation insulating layer measured from the substrate.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, wherein the height Ha is greater than a largest height of the isolation insulating layer measured from the substrate.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the first and second stressor layers include at least one of SiP, SiC and SiCP.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the first and second stressor layers includes SiGe.