# US 10,483,392 B2 · Capacitive tuning using backside gate

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- Number: US 10,483,392 B2
- Document ID: US10483392B2
- Status: Granted
- Kind: B2
- Application number: 15/988,987
- Filed: 2018-05-24
- Published: 2019-06-20
- Granted: 2019-11-19
- Earliest claimed: 2017-12-15
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Ravi Pramod Kumar Vedula
- Web page: https://patentgrep.com/patent/US10483392B2

## CPC

- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10P 72/7426: {used as a support during build up manufacturing of active devices}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10W 44/248: {for antennas}
- H10W 72/90: Bond pads, in general
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A radio frequency (RF) integrated circuit (RFIC) switch multi-finger transistor includes a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate. The RFIC also includes a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate. The second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC switch multi-finger transistor.

## Claims

### Claim 1

A balanced radio frequency (RF) integrated circuit (RFIC) including a stack of switch multi-finger transistors, comprising:
a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate;
a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, and a fourth gate with a fourth gate length on the second side of the substrate, in which the second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC; and
a dielectric layer on the second side of the substrate and in contact with the second gate and the fourth gate.

### Claim 2 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, in which a percentage of overlap between the second gate and a channel region of the first dual gate transistor is less than a percentage of overlap between the fourth gate and a channel region of the second dual gate transistor.

### Claim 3 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, in which the first side is a front-side of the substrate and the second side is a backside of the substrate.

### Claim 4 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, in which the first gate length is equal to the third gate length.

### Claim 5 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, in which the first gate length is different than the third gate length.

### Claim 6 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, in which the first gate length is different than the second gate length.

### Claim 7 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, in which the third gate length is different than the fourth gate length.

### Claim 8 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, in which the substrate comprises a semiconductor on insulator (SOI) substrate, having an SOI layer as the first side of the substrate and an isolation layer as the second side of the substrate.

### Claim 9 (depends on 1)

The RFIC including the stack of switch multi-finger transistors of claim 1, integrated into an RF front end module chip, the RF front end module chip incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

### Claim 10

A method of constructing a balanced radio frequency (RF) integrated circuit (RFIC) including a stack of switch multi-finger transistors, comprising:
fabricating a first dual gate transistor having a first gate with a first gate length on a first side of a substrate supported by a sacrificial substrate;
fabricating a second dual gate transistor having a third gate with a third gate length on the first side of the substrate and adjacent to the first dual gate transistor;
depositing a first side dielectric layer on the first dual gate transistor and the second dual gate transistor;
bonding a handle substrate to the first side dielectric layer;
removing the sacrificial substrate;
fabricating a second gate, with a second gate length, of the first dual gate transistor on a second side opposite the first side of the substrate and overlapping with the first gate;
fabricating a fourth gate, with a fourth gate length, of the second dual gate transistor on the second side of the substrate and overlapping with the third gate, in which the second gate length is different than the fourth gate length; and
depositing a dielectric layer on the second side of the substrate and in contact with the second gate and the fourth gate.

### Claim 11 (depends on 10)

The method of claim 10, in which the first side is a front-side of the substrate and the second side is a backside of the substrate.

### Claim 12 (depends on 10)

The method of claim 10, in which the first gate length is equal to the third gate length.

### Claim 13 (depends on 10)

The method of claim 10, in which the first gate length is different than the third gate length.

### Claim 14 (depends on 10)

The method of claim 10, further comprising integrating the RFIC into an RF front end module, the RF front end module incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.

### Claim 15

A radio frequency (RF) front end module, comprising:
an RF integrated circuit (RFIC) including a stack of switch multi-finger transistors comprising a first dual gate transistor having a first gate with a first gate length on a first side of a substrate, and a second gate with a second gate length on a second side of the substrate, and a second dual gate transistor having a third gate with a third gate length on the first side of the substrate, a fourth gate with a fourth gate length on the second side of the substrate, in which the second gate length is different than the fourth gate length, and the second dual gate transistor is coupled in series with the first dual gate transistor in the RFIC switch multi-finger transistor, and a dielectric layer on the second side of the substrate and in contact with the second gate and the fourth gate; and
an antenna coupled to the RFIC.

### Claim 16 (depends on 15)

The RF front end module of claim 15, in which the substrate comprises a semiconductor on insulator (SOI) substrate, having an SOI layer as the first side of the substrate and an isolation layer as the second side of the substrate.

### Claim 17 (depends on 15)

The RF front end module of claim 15, in which the first gate length is equal to the third gate length.

### Claim 18 (depends on 15)

The RF front end module of claim 15, in which the first gate length is different than the third gate length.

### Claim 19 (depends on 15)

The RF front end module of claim 15, in which a percentage of overlap between the second gate and a channel region of the first dual gate transistor is less than a percentage of overlap between the fourth gate and a channel region of the second dual gate transistor.

### Claim 20 (depends on 15)

The RF front end module of claim 15, integrated in a chip, incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone, and a portable computer.